Generated by EASE/HDL for peterj on Mon Jul 02 10:55:29 2007

Documentation for architecture MROD_X_Out/NAndG2/a0

Contents Side Data Generated HDL

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- Architecture 'a0' of 'NAndG2.
    3  --------------------------------------------------------------------------------
    4  -- Copy of the interface declaration of Entity 'NAndG2' :
    5  -- 
    6  --   port(
    7  --     An : in     std_logic;
    8  --     Bn : in     std_logic;
    9  --     O  : out    std_logic);
   10  -- 
   11  -- EASE/HDL end ----------------------------------------------------------------
   12  
   13  architecture a0 of NAndG2 is
   14  
   15  BEGIN
   16     O <= NOT(An And Bn);
   17  end architecture a0 ; -- of NAndG2
   18