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MROD_X_Out

CTRL_Logic

Documentation for architecture MROD_X_Out/CTRL_Logic/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- Architecture 'a0' of 'CTRL_Logic.
    3  --------------------------------------------------------------------------------
    4  -- Copy of the interface declaration of Entity 'CTRL_Logic' :
    5  -- 
    6  --   port(
    7  --     Adr1   : in     std_logic;
    8  --     CTRL_n : out    std_logic;
    9  --     MS3_n  : in     std_logic;
   10  --     Wr_n   : in     std_logic);
   11  -- 
   12  -- EASE/HDL end ----------------------------------------------------------------
   13  
   14  architecture a0 of CTRL_Logic is
   15  
   16  BEGIN
   17     Process (Wr_n, MS3_n, Adr1)
   18     Begin
   19        If Wr_n = '0' And MS3_n = '0' And Adr1 = '1' Then
   20           CTRL_n <= '0';
   21        Else
   22           CTRL_n <= '1';
   23        End If;
   24     End Process;
   25  end architecture a0 ; -- of CTRL_Logic
   26