Generated by EASE/HDL for peterj on Mon Jul 02 10:55:30 2007 |
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Contents | Side Data | Generated HDL |
1 -- EASE/HDL begin -------------------------------------------------------------- 2 -- 3 -- Architecture 'a0' of entity 'SelHold_IRQ'. 4 -- 5 -------------------------------------------------------------------------------- 6 -- 7 -- Copy of the interface declaration: 8 -- 9 -- port( 10 -- Clk : in std_logic; 11 -- Clr_n : in std_logic; 12 -- Rst_n : in std_logic; 13 -- Sel_IRQ : in std_logic_vector(2 downto 0); 14 -- Trig : in std_logic; 15 -- VME_IRQ_n : out std_logic_vector(7 downto 1)); 16 -- 17 -- EASE/HDL end ---------------------------------------------------------------- 18 19 architecture a0 of SelHold_IRQ is 20 21 begin 22 --Sel_IRQ determines the Level of the intterupt to be asserted. 23 Process (Clk, Rst_n) 24 Variable IRQ_Stat_n: Std_Logic_Vector(7 Downto 1); 25 Begin 26 If Rst_n = '0' Then 27 IRQ_Stat_n := (Others => '1'); 28 ElsIf Clk = '1' And Clk'Event Then 29 --Set has preference over Clear! 30 --Ony Trigger an interrupt when there is no 31 --interrupt pending (IRQ_Stat_n = "1111111") 32 If Trig = '1' And IRQ_Stat_n = "1111111" then 33 Case Sel_IRQ Is 34 When "111" => 35 IRQ_Stat_n(7) := '0'; 36 When "110" => 37 IRQ_Stat_n(6) := '0'; 38 When "101" => 39 IRQ_Stat_n(5) := '0'; 40 When "100" => 41 IRQ_Stat_n(4) := '0'; 42 When "011" => 43 IRQ_Stat_n(3) := '0'; 44 When "010" => 45 IRQ_Stat_n(2) := '0'; 46 When "001" => 47 IRQ_Stat_n(1) := '0'; 48 --Note that "000" decodes to the highest 49 --priority VME interrupt (Level 7) 50 When Others => 51 IRQ_Stat_n(7) := '0'; 52 End Case; 53 ElsIf Clr_n = '0' Then 54 IRQ_Stat_n := (Others => '1'); 55 End If; 56 End If; 57 VME_IRQ_n <= IRQ_Stat_n; 58 End Process; 59 end architecture a0 ; -- of SelHold_IRQ 60