Generated by EASE/HDL for peterj on Mon Jul 02 10:55:27 2007
Back Index MROD_X_Out Inv1

Documentation for architecture MROD_X_Out/Inv1/a0

Contents Side Data Generated HDL

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'Inv1'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     I : in     std_logic;
   11  --     O : out    std_logic);
   12  -- 
   13  -- EASE/HDL end ----------------------------------------------------------------
   14  
   15  architecture a0 of Inv1 is
   16  
   17  BEGIN
   18     O <= NOT I;
   19  end architecture a0 ; -- of Inv1
   20