Generated by EASE/HDL for peterj on Mon Jul 02 10:55:30 2007

Documentation for architecture MROD_X_Out/Sel_DTACK_BERR/a0

Contents Side Data Generated HDL

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'Sel_DTACK_BERR'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     DSB        : in     std_logic;
   11  --     Ready      : in     std_logic;
   12  --     SelBERR    : out    std_logic;
   13  --     SelDTACK   : out    std_logic;
   14  --     SlaveErr_n : in     std_logic;
   15  --     SlaveHit_n : in     std_logic);
   16  -- 
   17  -- EASE/HDL end ----------------------------------------------------------------
   18  
   19  architecture a0 of Sel_DTACK_BERR is
   20  
   21  begin
   22     Process (DSB, SlaveHit_n, SlaveErr_n, Ready)
   23     Begin
   24        If DSB = '1' And SlaveHit_n = '0' And Ready = '1' Then
   25           If SlaveErr_n = '1' Then
   26              SelDTACK <= '1';
   27              SelBERR <= '0';
   28           Else
   29              SelDTACK <= '0';
   30              SelBERR <= '1';
   31           End If;
   32        Else
   33           SelDTACK <= '0';
   34           SelBERR <= '0';
   35        End If;
   36     End Process;
   37  end architecture a0 ; -- of Sel_DTACK_BERR
   38