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MROD_X_Out

InternalReadyDecoder

Documentation for architecture MROD_X_Out/InternalReadyDecoder/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'InternalReadyDecoder'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     Cs_CR_CSR_n : in     std_logic;
   11  --     Cs_IRQ_n    : in     std_logic;
   12  --     DSB         : in     std_logic;
   13  --     LocBG_n     : in     std_logic;
   14  --     Ready       : out    std_logic);
   15  -- 
   16  -- EASE/HDL end ----------------------------------------------------------------
   17  
   18  architecture a0 of InternalReadyDecoder is
   19  
   20  BEGIN
   21     Process (DSB, LocBG_n,
   22              Cs_CR_CSR_n,
   23              Cs_IRQ_n)
   24     Begin
   25        If DSB = '1' And LocBG_n = '0' And
   26           (Cs_CR_CSR_n = '0' Or 
   27            Cs_IRQ_n = '0') Then
   28           Ready <= '1';
   29        Else
   30           Ready <= '0';
   31        End If; 
   32     End Process;
   33  end architecture a0 ; -- of InternalReadyDecoder
   34