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MROD_X_Out

CSR_BAR

Documentation for architecture MROD_X_Out/CSR_BAR/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'CSR_BAR'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     BAR             : out    std_logic_vector(7 downto 0);
   11  --     Clk             : in     std_logic;
   12  --     Cs_Bar_n        : in     std_logic;
   13  --     D               : in     std_logic_vector(7 downto 0);
   14  --     GAP_n           : in     std_logic;
   15  --     GA_n            : in     std_logic_vector(4 downto 0);
   16  --     InVME64xCrate_n : out    std_logic;
   17  --     JustBeforeDTACK : in     std_logic;
   18  --     LocalBAR        : in     std_logic_vector(4 downto 0);
   19  --     R_W_n           : in     std_logic;
   20  --     Reset           : in     std_logic);
   21  -- 
   22  -- EASE/HDL end ----------------------------------------------------------------
   23  
   24  architecture a0 of CSR_BAR is
   25     Signal ParErr: Std_Logic;
   26  BEGIN
   27     Process (GA_n, GAP_n)
   28        Variable Par: Std_Logic;
   29     Begin
   30        Par := '1';
   31        For I In 0 to 4 Loop
   32           Par := Par XOR GA_n(I);         
   33        End Loop;
   34        ParErr <= GAP_n XOR Par;
   35     End Process;
   36  
   37     --Upon Reset:
   38  
   39     --If module is in a VME64 crate then there is no Geographical addressing.
   40     --The GA_n pins will be open and pulled high. In this case take the LocalBAR
   41     --value (dip switches on the board) as BAR.
   42  
   43     --If module is in a VME64x crate with Geographical addressing (at least one of
   44     --the GA_n pins is low) then take the GA_n pins as BAR. But in case of a Parity
   45     --Error (ParErr = '1') then set the BAR to the "Amnesia Base Address" 0x1E.
   46     --(VME64x Recommendation 3.8).
   47  
   48     --The BAR addres is part of the CSR and is therefore writable.
   49     --Data from VMEbus can be written to the BAR when it is selected Cs_BAR_n asserted
   50  
   51     Process (Clk)
   52     Begin
   53        If Rising_Edge(Clk) Then
   54           --Reset is the synchronous command to load the BAR flip-flops
   55           If Reset= '1' Then
   56              If GA_n = "11111" Then
   57                 BAR(7 Downto 3) <= LocalBAR;
   58                 InVME64xCrate_n <= '1';
   59              ElsIf ParErr = '1' Then
   60                 BAR(7 Downto 3) <= Std_Logic_Vector(To_Unsigned(16#1E#,5));
   61                 InVME64xCrate_n <= '0';
   62              Else
   63                 BAR(7 Downto 3) <= NOT(GA_n);
   64                 InVME64xCrate_n <= '0';
   65              End If;
   66           ElsIf Cs_BAR_n = '0' And R_W_n = '0' And JustBeforeDTACK = '1' Then
   67              BAR(7 Downto 3) <= D(7 Downto 3);
   68              InVME64xCrate_n <= '0';
   69           End If;
   70        End If; 
   71        BAR(2 Downto 0) <= (Others => '0');
   72     End Process;
   73  end architecture a0 ; -- of CSR_BAR
   74