Documentation for architecture MROD_X_Out/AM_Decode/a0
VHDL Contents
1 architecture a0 of AM_Decode is
30
31 begin
32 Process (AM, IACK_n)
33 Variable AM_Code: Integer Range 16#3F# Downto 16#00#;
34 Begin
35 AM_Code := To_Integer(Unsigned(AM));
36
37 A64 <= '0';
38 A40 <= '0';
39 A32 <= '0';
40 A24 <= '0';
41 A16 <= '0';
42 USER_AM10 <= '0';
43
44 SUPER <= '0';
45 NPRIV <= '0';
46 PROG <= '0';
47 DATA <= '0';
48 BLT <= '0';
49 LOCK <= '0';
50 CR_CSR <= '0';
51 D64 <= '0';
52
53 If IACK_n = '1' Then
54 Case AM_Code Is
56 When 16#00# | 16#01# | 16#03# | 16#04# =>
58 A64 <= '1';
59 When 16#34# | 16#35# | 16#37# =>
61 A40 <= '1';
62 When 16#05# | 16#08# | 16#09# | 16#0A# | 16#0B# | 16#0C# | 16#0D# | 16#0E# | 16#0F# =>
64 A32 <= '1';
65 When 16#2F# | 16#32# |
67 16#38# | 16#39# | 16#3A# | 16#3B# | 16#3C# | 16#3D# | 16#3E# | 16#3F# =>
68 A24 <= '1';
69 When 16#29# | 16#2C# | 16#2D# =>
71 A16 <= '1';
72
73 When 16#10# =>
75 USER_AM10 <= '1';
76
77 When Others =>
85 End Case;
86
87
88 Case AM_Code Is
91 When 16#0C# | 16#0D# | 16#0E# | 16#0F# | 16#2D# | 16#3C# | 16#3D# | 16#3E# | 16#3F# =>
93 SUPER <= '1';
94 When Others =>
95 End Case;
96
97 Case AM_Code Is
98 When 16#08# | 16#09# | 16#0A# | 16#0B# | 16#29# | 16#38# | 16#39# | 16#3A# | 16#3B# =>
100 NPRIV <= '1';
101 When Others =>
102 End Case;
103
104 Case AM_Code Is
105 When 16#0A# | 16#0E# | 16#3A# | 16#3E# =>
107 PROG <= '1';
108 When Others =>
109 End Case;
110
111 Case AM_Code Is
112 When 16#09# | 16#0D# | 16#39# | 16#3d# =>
114 DATA <= '1';
115 When Others =>
116 End Case;
117
118 Case AM_Code Is
119 When 16#03# | 16#0B# | 16#0F# | 16#37# | 16#3B# | 16#3F# =>
121 BLT <= '1';
122 When Others =>
123 End Case;
124
125 Case AM_Code Is
126 When 16#04# | 16#05# | 16#2C# | 16#32# | 16#35# =>
128 LOCK <= '1';
129 When Others =>
130 End Case;
131
132 Case AM_Code Is
133 When 16#2F# =>
135 CR_CSR <= '1';
136 When Others =>
137 End Case;
138
139 Case AM_Code Is
140 When 16#00# | 16#08# | 16#0C# | 16#38# | 16#3C# =>
142 D64 <= '1';
143 When Others =>
144 End Case;
145 End If;
146 End Process;
147 end architecture a0 ;