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MROD_X_Out

UWEN_Logic

Documentation for architecture MROD_X_Out/UWEN_Logic/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'UWEN_Logic'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     Clk          : in     std_logic;
   11  --     Empty        : in     std_logic;
   12  --     LFF_n        : in     std_logic;
   13  --     RReq         : out    std_logic;
   14  --     Rst_n        : in     std_logic;
   15  --     Sync_LDOWN_n : in     std_logic;
   16  --     UWEN_n       : out    std_logic);
   17  -- 
   18  -- EASE/HDL end ----------------------------------------------------------------
   19  
   20  architecture a0 of UWEN_Logic is
   21  
   22  BEGIN
   23     Process (Clk, Rst_n)
   24     Begin
   25        If Rst_n = '0' Then
   26           UWEN_n <= '1';
   27           RReq <= '0';
   28        ElsIf Rising_Edge(Clk) Then
   29           If Sync_LDOWN_n = '1' And Empty = '0' And LFF_n = '1' Then
   30              UWEN_n <= '0';
   31              RReq <= '1';
   32           Else
   33              UWEN_n <= '1';
   34              RReq <= '0';
   35           End If;
   36        End If;
   37     End Process;
   38  end architecture a0 ; -- of UWEN_Logic
   39