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MROD_X_Out

SLink_FIFO

Documentation for architecture MROD_X_Out/SLink_FIFO/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'SLink_FIFO'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     Clock    : in     std_logic;
   11  --     Data     : in     std_logic_vector(32 downto 0);
   12  --     Empty    : out    std_logic;
   13  --     Full     : out    std_logic;
   14  --     HalfFull : out    std_logic;
   15  --     Q        : out    std_logic_vector(32 downto 0);
   16  --     RdReq    : in     std_logic;
   17  --     Rst_n    : in     std_logic;
   18  --     WrReq    : in     std_logic);
   19  -- 
   20  -- EASE/HDL end ----------------------------------------------------------------
   21  
   22  architecture a0 of SLink_FIFO is
   23  
   24    component scfifo_1024x33
   25      port (
   26      clk: IN std_logic;
   27      din: IN std_logic_VECTOR(32 downto 0);
   28      rd_en: IN std_logic;
   29      rst: IN std_logic;
   30      wr_en: IN std_logic;
   31      data_count: OUT std_logic_VECTOR(9 downto 0);
   32      dout: OUT std_logic_VECTOR(32 downto 0);
   33      empty: OUT std_logic;
   34      full: OUT std_logic);
   35    end component;
   36  
   37     signal Rst_Internal: std_logic;
   38     signal Usedw_Internal: std_logic_VECTOR (9 downto 0);
   39     signal Full_Internal: std_logic;
   40     
   41  begin
   42  
   43     Rst_Internal <= not Rst_n;
   44     HalfFull <= Usedw_Internal(9) or Full_Internal;  -- half full at 512 words
   45     Full <= Full_Internal;
   46     
   47     uc1: scfifo_1024x33
   48        port map (
   49           clk => Clock,
   50           din => Data,
   51           rd_en => RdReq,
   52           rst => Rst_Internal,
   53           wr_en => WrReq,
   54           data_count => Usedw_Internal,
   55           dout => Q,
   56           empty => Empty,
   57           full => Full_Internal
   58        );
   59  
   60  end architecture a0 ; -- of SLink_FIFO
   61  
   62