Generated by EASE/HDL for peterj on Mon Jul 02 10:55:29 2007 |
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Contents | Side Data | Generated HDL |
1 -- EASE/HDL begin -------------------------------------------------------------- 2 -- Architecture 'a0' of 'Pointer. 3 -------------------------------------------------------------------------------- 4 -- Copy of the interface declaration of Entity 'Pointer' : 5 -- 6 -- generic( 7 -- n : positive := 8 ); 8 -- port( 9 -- Clk : in std_logic; 10 -- En : in std_logic; 11 -- Q : out std_logic_vector(n-1 downto 0); 12 -- Rst_n : in std_logic); 13 -- 14 -- EASE/HDL end ---------------------------------------------------------------- 15 16 architecture a0 of Pointer is 17 18 BEGIN 19 Process (Clk, Rst_n, En) 20 Variable Count: Unsigned(n-1 DOWNTO 0); 21 Begin 22 If Rst_n = '0' Then 23 Count := (others => '0'); 24 ElsIf Clk = '1' And Clk'event Then 25 If En = '1' Then 26 Count := Count + 1; 27 End if; 28 End if; 29 Q <= Std_Logic_Vector(Count); 30 End Process; 31 end architecture a0 ; -- of Pointer 32