Generated by EASE/HDL for peterj on Mon Jul 02 10:55:29 2007
Documentation for architecture MROD_X_Out/My74ABT16543/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'My74ABT16543'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     A      : inout  std_logic_vector(15 downto 0);
   11  --     B      : inout  std_logic_vector(15 downto 0);
   12  --     CEAB_n : in     std_logic;
   13  --     CEBA_n : in     std_logic;
   14  --     LEAB_n : in     std_logic;
   15  --     LEBA_n : in     std_logic;
   16  --     OEAB_n : in     std_logic;
   17  --     OEBA_n : in     std_logic);
   18  -- 
   19  -- EASE/HDL end ----------------------------------------------------------------
   20  
   21  architecture a0 of My74ABT16543 is
   22      COMPONENT std543
   23      GENERIC (
   24          TimingModel     : STRING   := DefaultTimingModel
   25      );
   26      PORT (
   27          A                : INOUT std_logic := 'U';
   28          B                : INOUT std_logic := 'U';
   29          OEBANeg          : IN    std_logic := 'U';
   30          CEBANeg          : IN    std_logic := 'U';
   31          LEBANeg          : IN    std_logic := 'U';
   32          OEABNeg          : IN    std_logic := 'U';
   33          CEABNeg          : IN    std_logic := 'U';
   34          LEABNeg          : IN    std_logic := 'U'
   35          );
   36        END COMPONENT;
   37  
   38     --synopsys translate_off
   39     for all: std543 use entity fmf.std543(vhdl_behavioral);
   40     --synopsys translate_on
   41  
   42  begin
   43  
   44      bit15: std543
   45      generic map (
   46          TimingModel => "74ABT16543DGG")
   47      port map (
   48          A => A(15),
   49          B => B(15),
   50              OEBANeg => OEBA_n,
   51              CEBANeg => CEBA_n,
   52              LEBANeg => LEBA_n,
   53              OEABNeg => OEAB_n,
   54              CEABNeg => CEAB_n,
   55              LEABNeg => LEAB_n);
   56  
   57      bit14: std543
   58      generic map (
   59          TimingModel => "74ABT16543DGG")
   60      port map (
   61          A => A(14),
   62          B => B(14),
   63              OEBANeg => OEBA_n,
   64              CEBANeg => CEBA_n,
   65              LEBANeg => LEBA_n,
   66              OEABNeg => OEAB_n,
   67              CEABNeg => CEAB_n,
   68              LEABNeg => LEAB_n);
   69  
   70      bit13: std543
   71      generic map (
   72          TimingModel => "74ABT16543DGG")
   73      port map (
   74          A => A(13),
   75          B => B(13),
   76              OEBANeg => OEBA_n,
   77              CEBANeg => CEBA_n,
   78              LEBANeg => LEBA_n,
   79              OEABNeg => OEAB_n,
   80              CEABNeg => CEAB_n,
   81              LEABNeg => LEAB_n);
   82  
   83      bit12: std543
   84      generic map (
   85          TimingModel => "74ABT16543DGG")
   86      port map (
   87          A => A(12),
   88          B => B(12),
   89              OEBANeg => OEBA_n,
   90              CEBANeg => CEBA_n,
   91              LEBANeg => LEBA_n,
   92              OEABNeg => OEAB_n,
   93              CEABNeg => CEAB_n,
   94              LEABNeg => LEAB_n);
   95  
   96      bit11: std543
   97      generic map (
   98          TimingModel => "74ABT16543DGG")
   99      port map (
  100          A => A(11),
  101          B => B(11),
  102              OEBANeg => OEBA_n,
  103              CEBANeg => CEBA_n,
  104              LEBANeg => LEBA_n,
  105              OEABNeg => OEAB_n,
  106              CEABNeg => CEAB_n,
  107              LEABNeg => LEAB_n);
  108  
  109      bit10: std543
  110      generic map (
  111          TimingModel => "74ABT16543DGG")
  112      port map (
  113          A => A(10),
  114          B => B(10),
  115              OEBANeg => OEBA_n,
  116              CEBANeg => CEBA_n,
  117              LEBANeg => LEBA_n,
  118              OEABNeg => OEAB_n,
  119              CEABNeg => CEAB_n,
  120              LEABNeg => LEAB_n);
  121  
  122      bit9: std543
  123      generic map (
  124          TimingModel => "74ABT16543DGG")
  125      port map (
  126          A => A(9),
  127          B => B(9),
  128              OEBANeg => OEBA_n,
  129              CEBANeg => CEBA_n,
  130              LEBANeg => LEBA_n,
  131              OEABNeg => OEAB_n,
  132              CEABNeg => CEAB_n,
  133              LEABNeg => LEAB_n);
  134  
  135      bit8: std543
  136      generic map (
  137          TimingModel => "74ABT16543DGG")
  138      port map (
  139          A => A(8),
  140          B => B(8),
  141              OEBANeg => OEBA_n,
  142              CEBANeg => CEBA_n,
  143              LEBANeg => LEBA_n,
  144              OEABNeg => OEAB_n,
  145              CEABNeg => CEAB_n,
  146              LEABNeg => LEAB_n);
  147  
  148      bit7: std543
  149      generic map (
  150          TimingModel => "74ABT16543DGG")
  151      port map (
  152          A => A(7),
  153          B => B(7),
  154              OEBANeg => OEBA_n,
  155              CEBANeg => CEBA_n,
  156              LEBANeg => LEBA_n,
  157              OEABNeg => OEAB_n,
  158              CEABNeg => CEAB_n,
  159              LEABNeg => LEAB_n);
  160  
  161      bit6: std543
  162      generic map (
  163          TimingModel => "74ABT16543DGG")
  164      port map (
  165          A => A(6),
  166          B => B(6),
  167              OEBANeg => OEBA_n,
  168              CEBANeg => CEBA_n,
  169              LEBANeg => LEBA_n,
  170              OEABNeg => OEAB_n,
  171              CEABNeg => CEAB_n,
  172              LEABNeg => LEAB_n);
  173  
  174      bit5: std543
  175      generic map (
  176          TimingModel => "74ABT16543DGG")
  177      port map (
  178          A => A(5),
  179          B => B(5),
  180              OEBANeg => OEBA_n,
  181              CEBANeg => CEBA_n,
  182              LEBANeg => LEBA_n,
  183              OEABNeg => OEAB_n,
  184              CEABNeg => CEAB_n,
  185              LEABNeg => LEAB_n);
  186  
  187      bit4: std543
  188      generic map (
  189          TimingModel => "74ABT16543DGG")
  190      port map (
  191          A => A(4),
  192          B => B(4),
  193              OEBANeg => OEBA_n,
  194              CEBANeg => CEBA_n,
  195              LEBANeg => LEBA_n,
  196              OEABNeg => OEAB_n,
  197              CEABNeg => CEAB_n,
  198              LEABNeg => LEAB_n);
  199  
  200      bit3: std543
  201      generic map (
  202          TimingModel => "74ABT16543DGG")
  203      port map (
  204          A => A(3),
  205          B => B(3),
  206              OEBANeg => OEBA_n,
  207              CEBANeg => CEBA_n,
  208              LEBANeg => LEBA_n,
  209              OEABNeg => OEAB_n,
  210              CEABNeg => CEAB_n,
  211              LEABNeg => LEAB_n);
  212  
  213      bit2: std543
  214      generic map (
  215          TimingModel => "74ABT16543DGG")
  216      port map (
  217          A => A(2),
  218          B => B(2),
  219              OEBANeg => OEBA_n,
  220              CEBANeg => CEBA_n,
  221              LEBANeg => LEBA_n,
  222              OEABNeg => OEAB_n,
  223              CEABNeg => CEAB_n,
  224              LEABNeg => LEAB_n);
  225  
  226      bit1: std543
  227      generic map (
  228          TimingModel => "74ABT16543DGG")
  229      port map (
  230          A => A(1),
  231          B => B(1),
  232              OEBANeg => OEBA_n,
  233              CEBANeg => CEBA_n,
  234              LEBANeg => LEBA_n,
  235              OEABNeg => OEAB_n,
  236              CEABNeg => CEAB_n,
  237              LEABNeg => LEAB_n);
  238  
  239      bit0: std543
  240      generic map (
  241          TimingModel => "74ABT16543DGG")
  242      port map (
  243          A => A(0),
  244          B => B(0),
  245              OEBANeg => OEBA_n,
  246              CEBANeg => CEBA_n,
  247              LEBANeg => LEBA_n,
  248              OEABNeg => OEAB_n,
  249              CEABNeg => CEAB_n,
  250              LEABNeg => LEAB_n);
  251  
  252  end architecture a0 ; -- of My74ABT16543
  253