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MROD_X_Out

CSR_AddrDec

Documentation for architecture MROD_X_Out/CSR_AddrDec/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'CSR_AddrDec'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     Adr         : in     std_logic_vector(16 downto 0);
   11  --     Cs_Bar_n    : out    std_logic;
   12  --     Cs_BitClr_n : out    std_logic;
   13  --     Cs_BitSet_n : out    std_logic;
   14  --     Cs_CR_CSR_n : in     std_logic;
   15  --     Cs_CR_n     : out    std_logic);
   16  -- 
   17  -- EASE/HDL end ----------------------------------------------------------------
   18  
   19  architecture a0 of CSR_AddrDec is
   20  
   21  begin
   22     Process (Adr, Cs_CR_CSR_n)
   23     Begin
   24        Cs_BAR_n <= '1';
   25        Cs_BitClr_n <= '1';
   26        Cs_BitSet_n <= '1';
   27        Cs_CR_n <= '1';
   28  
   29        If Cs_CR_CSR_n = '0' Then
   30           --Bit Set Register 0x7FFFF shifted>>2 = 
   31           If Unsigned(Adr) = 16#1FFFF# Then
   32              Cs_BAR_n <= '0';
   33           --Bit Set Register 0x7FFFB shifted>>2 = 
   34           ElsIf Unsigned(Adr) = 16#1FFFE# Then
   35              Cs_BitSet_n <= '0';
   36           --Bit Clear Register 0x7FFF7 shifted>>2 = 
   37           ElsIf Unsigned(Adr) = 16#1FFFD# Then
   38              Cs_BitClr_n <= '0';
   39           --Defined Config ROM 0x01000 shifted>>2 = 
   40           ElsIf Unsigned(Adr) < 16#00400# Then
   41              Cs_CR_n <= '0';
   42           End If;
   43        End If;
   44     End Process;
   45  end architecture a0 ; -- of CSR_AddrDec
   46