Generated by EASE/HDL for peterj on Mon Jul 02 10:55:31 2007 |
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Contents | Side Data | Generated HDL |
1 -- EASE/HDL begin -------------------------------------------------------------- 2 -- Architecture 'a1' of 'StatusCounter. 3 -------------------------------------------------------------------------------- 4 -- Copy of the interface declaration of Entity 'StatusCounter' : 5 -- 6 -- generic( 7 -- NumWords : positive := 256 ; 8 -- NumWordsU : positive := 8 ); 9 -- port( 10 -- Clk : in std_logic; 11 -- Empty : out std_logic; 12 -- Full : out std_logic; 13 -- RReq : in std_logic; 14 -- Rst_n : in std_logic; 15 -- UsedW : out std_logic_vector(NumWordsU downto 0); 16 -- WReq : in std_logic); 17 -- 18 -- EASE/HDL end ---------------------------------------------------------------- 19 20 architecture a1 of StatusCounter is 21 BEGIN 22 Process (Clk, Rst_n) 23 --Note! Count width is NumWordsU and NOT NumWordsU-1 !! 24 --Fifo state can be filled up 2^NumWords plus empty! 25 Variable Count: Unsigned(NumWordsU Downto 0); 26 Begin 27 If Rst_n = '0' Then 28 Count := (Others => '0'); 29 Empty <= '1'; 30 Full <= '0'; 31 ElsIf Rising_Edge(Clk) Then 32 33 If WReq = '1' Then 34 Count := Count + 2; 35 End If; 36 37 If RReq = '1' Then 38 Count := Count - 1; 39 End If; 40 41 If To_Integer(Count) + 2 > NumWords Then 42 Full <= '1'; 43 Else 44 --To_Integer(Count) + 2 <= NumWords 45 Full <= '0'; 46 End If; 47 48 If To_Integer(Count) = 0 Then 49 Empty <= '1'; 50 Else 51 Empty <= '0'; 52 End If; 53 End If; 54 UsedW <= Std_Logic_Vector(Count); 55 End Process; 56 end architecture a1 ; -- of StatusCounter 57