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MROD_X_Out

My74ABT16245

Documentation for architecture MROD_X_Out/My74ABT16245/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'My74ABT16245'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     A   : inout  std_logic_vector(15 downto 0);
   11  --     B   : inout  std_logic_vector(15 downto 0);
   12  --     DIR : in     std_logic;
   13  --     E_n : in     std_logic);
   14  -- 
   15  -- EASE/HDL end ----------------------------------------------------------------
   16  
   17  architecture a0 of My74ABT16245 is
   18      COMPONENT std245
   19      GENERIC (
   20          TimingModel     : STRING   := DefaultTimingModel
   21      );
   22      PORT (
   23          A                : INOUT std_logic := 'U';
   24          B                : INOUT std_logic := 'U';
   25          ENeg             : IN    std_logic := 'U';
   26          DIR              : IN    std_logic := 'U'
   27          );
   28      END COMPONENT;
   29  
   30      --synopsys translate_off
   31      for all: std245 use entity fmf.std245(vhdl_behavioral);
   32      --synopsys translate_on
   33  
   34  begin
   35  
   36      bit15: std245
   37      generic map (
   38          TimingModel => "74ABT16245BDDG")
   39      port map (
   40          A => A(15),
   41          B => B(15),
   42              ENeg => E_n,
   43              DIR => DIR);
   44  
   45      bit14: std245
   46      generic map (
   47          TimingModel => "74ABT16245BDDG")
   48      port map (
   49          A => A(14),
   50          B => B(14),
   51          ENeg => E_n,
   52              DIR => DIR);
   53      bit13: std245
   54      generic map (
   55          TimingModel => "74ABT16245BDDG")
   56      port map (
   57          A => A(13),
   58          B => B(13),
   59          ENeg => E_n,
   60              DIR => DIR);
   61      bit12: std245
   62      generic map (
   63          TimingModel => "74ABT16245BDDG")
   64      port map (
   65          A => A(12),
   66          B => B(12),
   67          ENeg => E_n,
   68              DIR => DIR);
   69      bit11: std245
   70      generic map (
   71          TimingModel => "74ABT16245BDDG")
   72      port map (
   73          A => A(11),
   74          B => B(11),
   75          ENeg => E_n,
   76              DIR => DIR);
   77      bit10: std245
   78      generic map (
   79          TimingModel => "74ABT16245BDDG")
   80      port map (
   81          A => A(10),
   82          B => B(10),
   83          ENeg => E_n,
   84              DIR => DIR);
   85      bit9: std245
   86      generic map (
   87          TimingModel => "74ABT16245BDDG")
   88      port map (
   89          A => A(9),
   90          B => B(9),
   91          ENeg => E_n,
   92              DIR => DIR);
   93      bit8: std245
   94      generic map (
   95          TimingModel => "74ABT16245BDDG")
   96      port map (
   97          A => A(8),
   98          B => B(8),
   99          ENeg => E_n,
  100              DIR => DIR);
  101      bit7: std245
  102      generic map (
  103          TimingModel => "74ABT16245BDDG")
  104      port map (
  105          A => A(7),
  106          B => B(7),
  107          ENeg => E_n,
  108              DIR => DIR);
  109      bit6: std245
  110      generic map (
  111          TimingModel => "74ABT16245BDDG")
  112      port map (
  113          A => A(6),
  114          B => B(6),
  115          ENeg => E_n,
  116              DIR => DIR);
  117      bit5: std245
  118      generic map (
  119          TimingModel => "74ABT16245BDDG")
  120      port map (
  121          A => A(5),
  122          B => B(5),
  123          ENeg => E_n,
  124              DIR => DIR);
  125      bit4: std245
  126      generic map (
  127          TimingModel => "74ABT16245BDDG")
  128      port map (
  129          A => A(4),
  130          B => B(4),
  131          ENeg => E_n,
  132              DIR => DIR);
  133      bit3: std245
  134      generic map (
  135          TimingModel => "74ABT16245BDDG")
  136      port map (
  137          A => A(3),
  138          B => B(3),
  139          ENeg => E_n,
  140              DIR => DIR);
  141      bit2: std245
  142      generic map (
  143          TimingModel => "74ABT16245BDDG")
  144      port map (
  145          A => A(2),
  146          B => B(2),
  147          ENeg => E_n,
  148              DIR => DIR);
  149      bit1: std245
  150      generic map (
  151          TimingModel => "74ABT16245BDDG")
  152      port map (
  153          A => A(1),
  154          B => B(1),
  155          ENeg => E_n,
  156              DIR => DIR);
  157      bit0: std245
  158      generic map (
  159          TimingModel => "74ABT16245BDDG")
  160      port map (
  161          A => A(0),
  162          B => B(0),
  163          ENeg => E_n,
  164              DIR => DIR);
  165  end architecture a0 ; -- of My74ABT16245
  166