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MROD_X_Out

Adr_Latch_Count

Documentation for architecture MROD_X_Out/Adr_Latch_Count/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'Adr_Latch_Count'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   generic(
   10  --     Width :  positive := 11);
   11  --   port(
   12  --     AD_PHASE : in     std_logic;
   13  --     BLT      : in     std_logic;
   14  --     Clk      : in     std_logic;
   15  --     DS1      : in     std_logic;
   16  --     DSB_End  : in     std_logic;
   17  --     Inc1     : in     std_logic;
   18  --     Inc2     : in     std_logic;
   19  --     Inc4     : in     std_logic;
   20  --     Inc8     : in     std_logic;
   21  --     LADI     : in     std_logic;
   22  --     LOC_A    : out    std_logic_vector(Width-1 downto 1);
   23  --     Rst_n    : in     std_logic;
   24  --     VME_A    : in     std_logic_vector(31 downto 1));
   25  -- 
   26  -- EASE/HDL end ----------------------------------------------------------------
   27  
   28  architecture a0 of Adr_Latch_Count is
   29  begin
   30     Process(Clk, Rst_n)
   31        Variable Cnt: Unsigned(Width - 1 Downto 1);
   32     Begin
   33        If Rst_n = '0' Then
   34           Cnt := (Others => '0');
   35        ElsIf Rising_Edge(Clk) Then
   36           --Flow Through when LADI inactive
   37           If LADI = '0' Then
   38              Cnt := Unsigned(VME_A(Width - 1 Downto 1));
   39  
   40           --Increment the address counter with the proper amount 
   41           --LWORD_n, A1, DS1_n and DS0_n (Byte Enable Decoder).
   42           --Only increment when this is NOT the Addres Phase of the transfer
   43           --and this is a BLT or MBLT (=D64) cycle.
   44           ElsIf AD_PHASE = '0' And BLT = '1' AND DSB_End = '1' Then
   45              --Note that Inc1 needs special attention. During Single Byte Block
   46              --Transfers, address line 0 is encoded in DS1_n, and DS0_n.
   47              --The address counter bits [63..1] should only be incremented when
   48              --a word boundary (2 bytes) is crossed. This has the effect that during 
   49              --a Single Byte Block Transfer the address counter is only incremented once
   50              --every two cycles. Wheter the address counter is to be incremented after 
   51              --the very first cycle of the block transfer depends on wether the even or
   52              --the odd byte is transferred first (status of DS1).
   53              If Inc1 = '1' Then
   54                 If DS1 = '0' Then
   55                    Cnt := Cnt + 1;
   56                 End If;
   57              --Note that Inc2, Inc4 and Inc8 increment by 1, 2 and 4 respectively.
   58              --This is because bit 0 is missing!
   59              ElsIf Inc2 = '1' Then
   60                 Cnt := Cnt + 1;
   61              ElsIf Inc4 = '1' Then
   62                 Cnt := Cnt + 2;
   63              ElsIf Inc8 = '1' Then
   64                 Cnt := Cnt + 4;
   65              End If;
   66           End If;
   67        End If;
   68        LOC_A <= Std_Logic_Vector(Cnt);
   69     End Process;
   70  end architecture a0 ; -- of Adr_Latch_Count
   71