Back

Index

MROD_X_Out

RegNoRst

Documentation for architecture MROD_X_Out/RegNoRst/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'RegNoRst'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     Clk : in     std_logic;
   11  --     D   : in     std_logic;
   12  --     Q   : out    std_logic := '0');
   13  -- 
   14  -- EASE/HDL end ----------------------------------------------------------------
   15  
   16  architecture a0 of RegNoRst is
   17  
   18  BEGIN
   19     Process (Clk)
   20     Begin
   21        If Rising_Edge(Clk) Then
   22           Q <= D;
   23        End If;    
   24     End Process;
   25  end architecture a0 ; -- of RegNoRst
   26