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MROD_X_Out

HoldFF

Documentation for architecture MROD_X_Out/HoldFF/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'HoldFF'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     Clk   : in     std_logic;
   11  --     D     : in     std_logic;
   12  --     Q     : out    std_logic;
   13  --     Res   : in     std_logic;
   14  --     Rst_n : in     std_logic);
   15  -- 
   16  -- EASE/HDL end ----------------------------------------------------------------
   17  
   18  architecture a0 of HoldFF is
   19  
   20  BEGIN
   21     Process (Clk, Rst_n)
   22     Begin
   23        If Rst_n = '0' Then
   24           Q <= '0';
   25        ElsIf Clk = '1' And Clk'Event Then
   26           --Set has preference over Reset!
   27           If D = '1' then
   28              Q <= '1';
   29           ElsIf Res = '1' Then
   30              Q <= '0';
   31           End If;
   32        End If;  
   33     End Process;
   34  end architecture a0 ; -- of HoldFF
   35