Generated by EASE/HDL for peterj on Mon Jul 02 10:55:25 2007 |
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Contents | Side Data | Generated HDL |
1 -- EASE/HDL begin -------------------------------------------------------------- 2 -- 3 -- Architecture 'a0' of entity 'CR_CSR_DataMux'. 4 -- 5 -------------------------------------------------------------------------------- 6 -- 7 -- Copy of the interface declaration: 8 -- 9 -- port( 10 -- BAR : in std_logic_vector(7 downto 0); 11 -- CR_CSR_D : out std_logic_vector(7 downto 0); 12 -- CR_Data : in std_logic_vector(7 downto 0); 13 -- Cs_Bar_n : in std_logic; 14 -- Cs_BitClr_n : in std_logic; 15 -- Cs_BitSet_n : in std_logic; 16 -- Cs_CR_n : in std_logic; 17 -- Q_BitSetClr : in std_logic_vector(7 downto 0)); 18 -- 19 -- EASE/HDL end ---------------------------------------------------------------- 20 21 architecture a0 of CR_CSR_DataMux is 22 23 begin 24 Process(Cs_BitSet_n, Cs_BitClr_n, Cs_Bar_n, Cs_CR_n, 25 Q_BitSetClr, BAR, CR_Data) 26 Begin 27 If Cs_BAR_n = '0' Then 28 CR_CSR_D <= BAR; 29 ElsIf Cs_BitSet_n = '0' Then 30 CR_CSR_D <= Q_BitSetClr; 31 ElsIf Cs_BitClr_n = '0' Then 32 CR_CSR_D <= Q_BitSetClr; 33 ElsIf Cs_CR_n = '0' Then 34 CR_CSR_D <= CR_Data; 35 Else 36 --All reserved or unimplemented locations in the Defined CR Area 37 --shall read as 0x00 (VME64x Rule 10.2) 38 --All unimplemented locations in the Defined CSR Area shall Read 39 --as 0x00 (VME64x Rule 10.14) 40 CR_CSR_D <= (Others => '0'); 41 End If; 42 End Process; 43 end architecture a0 ; -- of CR_CSR_DataMux 44