Documentation for architecture MROD_X_Out/SlowRegMux/a0
VHDL Contents
1 architecture a0 of SlowRegMux is
106
107 begin
108
109 Process (Reg0d, Reg1d, Reg2d, Reg3d, Reg4d, Reg5d, Reg6d, Reg7d,
110 Reg8d, Reg9d, RegAd, RegBd, RegCd, RegDd, RegEd, RegFd,
111 Reg10d, Reg11d, Reg12d, Reg13d, Reg14d, Reg15d, Reg16d, Reg17d,
112 Reg18d, Reg19d, Reg1Ad, Reg1Bd, Reg1Cd, Reg1Dd, Reg1Ed, Reg1Fd,
113 Reg20d, Reg21d, Reg22d, Reg23d, Reg24d, Reg25d, Reg26d, Reg27d,
114 Reg28d, Reg29d, Reg2Ad, Reg2Bd, Reg2Cd, Reg2Dd,
115 Reg3Fd, Sel0_n, Sel1_n, Sel2_n, Sel3_n, Sel4_n, Sel5_n, Sel6_n, Sel7_n,
117 Sel8_n, Sel9_n, SelA_n, SelB_n, SelC_n, SelD_n, SelE_n, SelF_n,
118 Sel10_n, Sel11_n, Sel12_n, Sel13_n, Sel14_n, Sel15_n, Sel16_n, Sel17_n,
119 Sel18_n, Sel19_n, Sel1A_n, Sel1B_n, Sel1C_n, Sel1D_n, Sel1E_n, Sel1F_n,
120 Sel20_n, Sel21_n, Sel22_n, Sel23_n, Sel24_n, Sel25_n, Sel26_n, Sel27_n,
121 Sel28_n, Sel29_n, Sel2A_n, Sel2B_n, Sel2C_n, Sel2D_n,
122 Sel3F_n) Begin
124 If Sel0_n = '0' Then
125 D_Regs(31 Downto 11) <= (Others => '0');
126 D_Regs(10 Downto 0) <= Reg0d;
127 ElsIf Sel1_n = '0' Then
128 D_Regs <= Reg1d;
129 ElsIf Sel2_n = '0' Then
130 D_Regs(31 Downto 11) <= (Others => '0');
131 D_Regs(10 Downto 0) <= Reg2d;
132 ElsIf Sel3_n = '0' Then
133 D_Regs(31 Downto 12) <= (Others => '0');
134 D_Regs(11 Downto 0) <= Reg3d;
135 ElsIf Sel4_n = '0' Then
136 D_Regs(31 Downto 24) <= (Others => '0');
137 D_Regs(23 Downto 0) <= Reg4d;
138 ElsIf Sel5_n = '0' Then
139 D_Regs(31 Downto 0) <= Reg5d;
140 ElsIf Sel6_n = '0' Then
141 D_Regs(31 Downto 0) <= Reg6d;
142 ElsIf Sel7_n = '0' Then
143 D_Regs(31 Downto 0) <= Reg7d;
144 ElsIf Sel8_n = '0' Then
145 D_Regs(31 Downto 4) <= (Others => '0');
146 D_Regs(3 Downto 0) <= Reg8d;
147 ElsIf Sel9_n = '0' Then
148 D_Regs(31 Downto 25) <= (Others => '0');
149 D_Regs(24 Downto 0) <= Reg9d;
150 ElsIf SelA_n = '0' Then
151 D_Regs(31 Downto 0) <= RegAd;
152 ElsIf SelB_n = '0' Then
153 D_Regs(31 Downto 0) <= RegBd;
154 ElsIf SelC_n = '0' Then
155 D_Regs(31 Downto 0) <= RegCd;
156 ElsIf SelD_n = '0' Then
157 D_Regs(31 Downto 0) <= RegDd;
158 ElsIf SelE_n = '0' Then
159 D_Regs(31 Downto 0) <= RegEd;
160 ElsIf SelF_n = '0' Then
161 D_Regs(31 Downto 1) <= (Others => '0');
162 D_Regs(0) <= RegFd;
163 ElsIf Sel10_n = '0' Then
164 D_Regs(31 Downto 0) <= Reg10d;
165 ElsIf Sel11_n = '0' Then
166 D_Regs(31 Downto 1) <= (Others => '0');
167 D_Regs(0) <= Reg11d;
168 ElsIf Sel12_n = '0' Then
169 D_Regs(31 Downto 0) <= Reg12d;
170 ElsIf Sel13_n = '0' Then
171 D_Regs(31 Downto 1) <= (Others => '0');
172 D_Regs(0) <= Reg13d;
173 ElsIf Sel14_n = '0' Then
174 D_Regs(31 Downto 0) <= Reg14d;
175 ElsIf Sel15_n = '0' Then
176 D_Regs(31 Downto 1) <= (Others => '0');
177 D_Regs(0) <= Reg15d;
178 ElsIf Sel16_n = '0' Then
179 D_Regs(31 Downto 0) <= Reg16d;
180 ElsIf Sel17_n = '0' Then
181 D_Regs(31 Downto 1) <= (Others => '0');
182 D_Regs(0) <= Reg17d;
183 ElsIf Sel18_n = '0' Then
184 D_Regs(31 Downto 0) <= Reg18d;
185 ElsIf Sel19_n = '0' Then
186 D_Regs(31 Downto 1) <= (Others => '0');
187 D_Regs(0) <= Reg19d;
188 ElsIf Sel1A_n = '0' Then
189 D_Regs(31 Downto 0) <= Reg1Ad;
190 ElsIf Sel1B_n = '0' Then
191 D_Regs(31 Downto 1) <= (Others => '0');
192 D_Regs(0) <= Reg1Bd;
193 ElsIf Sel1C_n = '0' Then
194 D_Regs(31 Downto 0) <= Reg1Cd;
195 ElsIf Sel1D_n = '0' Then
196 D_Regs(31 Downto 1) <= (Others => '0');
197 D_Regs(0) <= Reg1Dd;
198 ElsIf Sel1E_n = '0' Then
199 D_Regs(31 Downto 0) <= Reg1Ed;
200 ElsIf Sel1F_n = '0' Then
201 D_Regs(31 Downto 1) <= (Others => '0');
202 D_Regs(0) <= Reg1Fd;
203 ElsIf Sel20_n = '0' Then
204 D_Regs(31 Downto 0) <= Reg20d;
205 ElsIf Sel21_n = '0' Then
206 D_Regs(31 Downto 1) <= (Others => '0');
207 D_Regs(0) <= Reg21d;
208 ElsIf Sel22_n = '0' Then
209 D_Regs(31 Downto 0) <= Reg22d;
210 ElsIf Sel23_n = '0' Then
211 D_Regs(31 Downto 1) <= (Others => '0');
212 D_Regs(0) <= Reg23d;
213 ElsIf Sel24_n = '0' Then
214 D_Regs(31 Downto 0) <= Reg24d;
215 ElsIf Sel25_n = '0' Then
216 D_Regs(31 Downto 1) <= (Others => '0');
217 D_Regs(0) <= Reg25d;
218 ElsIf Sel26_n = '0' Then
219 D_Regs(31 Downto 0) <= Reg26d;
220 ElsIf Sel27_n = '0' Then
221 D_Regs(31 Downto 1) <= (Others => '0');
222 D_Regs(0) <= Reg27d;
223 ElsIf Sel28_n = '0' Then
224 D_Regs(31 Downto 0) <= Reg28d;
225 ElsIf Sel29_n = '0' Then
226 D_Regs(31 Downto 1) <= (Others => '0');
227 D_Regs(0) <= Reg29d;
228 ElsIf Sel2A_n = '0' Then
229 D_Regs <= Reg2Ad;
230 ElsIf Sel2B_n = '0' Then
231 D_Regs(31 Downto 24) <= Reg2Bd;
232 D_Regs(23 Downto 0) <= (Others => '0');
233 ElsIf Sel2C_n = '0' Then
234 D_Regs <= Reg2Cd;
235 ElsIf Sel2D_n = '0' Then
236 D_Regs <= Reg2Dd;
237
238 ElsIf Sel3F_n = '0' Then D_Regs(31 Downto 26) <= (Others => '0');
240 D_Regs(25 downto 0) <= Reg3Fd;
241 Else
242 D_Regs <= (Others => '0');
243 End If;
244 End Process;
245
246 end architecture a0 ;