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MROD_X_Out

Hold_WRITE

Documentation for architecture MROD_X_Out/Hold_WRITE/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'Hold_WRITE'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     Clk     : in     std_logic;
   11  --     DSB     : in     std_logic;
   12  --     R_W_n   : out    std_logic;
   13  --     Rst_n   : in     std_logic;
   14  --     WRITE_n : in     std_logic);
   15  -- 
   16  -- EASE/HDL end ----------------------------------------------------------------
   17  
   18  architecture a0 of Hold_WRITE is
   19  
   20  begin
   21     Process (Clk, Rst_n)
   22     Begin
   23        If Rst_n = '0' Then
   24           R_W_n <= '1';
   25        ElsIf Rising_Edge(Clk) Then
   26           --the R_W_n signal is continuously updated but as soon as the
   27           --DSB signal arrives the result is holded for the duration of DSB
   28           If DSB = '0' Then
   29              If WRITE_n = '0' Then
   30                 R_W_n <= '0';
   31              Else
   32                 R_W_n <= '1';
   33              End If;
   34           End If;
   35        End If;
   36     End Process;
   37  end architecture a0 ; -- of Hold_WRITE
   38