Back

Index

MROD_X_Out

Dec_TstA64

Documentation for architecture MROD_X_Out/Dec_TstA64/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- Architecture 'a0' of 'Dec_TstA64.
    3  --------------------------------------------------------------------------------
    4  -- Copy of the interface declaration of Entity 'Dec_TstA64' :
    5  -- 
    6  --   port(
    7  --     A64         : in     std_logic;
    8  --     Clk         : in     std_logic;
    9  --     Cs_TstA64_n : out    std_logic;
   10  --     D64         : in     std_logic;
   11  --     DECODE      : in     std_logic;
   12  --     Rst_n       : in     std_logic);
   13  -- 
   14  -- EASE/HDL end ----------------------------------------------------------------
   15  
   16  architecture a0 of Dec_TstA64 is
   17  
   18  begin
   19     Process (Clk, Rst_n)
   20     Begin
   21        If Rst_n = '0' Then
   22           CS_TstA64_n <= '1';
   23        ElsIf Rising_Edge(Clk) Then
   24           --the Chip Select signal is continuously updated but as soon as the
   25           --DECODE signal arrives the result is holded for the duration of DECODE
   26           If DECODE = '0' Then
   27              If A64 = '1' And D64 = '1' Then
   28                 CS_TstA64_n <= '0';
   29              Else
   30                 CS_TstA64_n <= '1';
   31              End If;
   32           End If;
   33        End If;
   34     End Process;
   35  end architecture a0 ; -- of Dec_TstA64
   36