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MROD_X_Out

CR_1024x8

Documentation for architecture MROD_X_Out/CR_1024x8/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'CR_1024x8'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     Address : in     std_logic_vector(9 downto 0);
   11  --     Clk     : in     std_logic;
   12  --     Q       : out    std_logic_vector(7 downto 0));
   13  -- 
   14  -- EASE/HDL end ----------------------------------------------------------------
   15  
   16  architecture a0 of CR_1024x8 is
   17     component rom_1024x8
   18        port (
   19           addr: IN std_logic_VECTOR(9 downto 0);
   20           clk: IN std_logic;
   21           dout: OUT std_logic_VECTOR(7 downto 0));
   22     end component;
   23  Begin
   24     Inst_1: rom_1024x8
   25        Port Map (
   26           addr => Address,
   27           clk => Clk,
   28           dout => Q);
   29  end architecture a0 ; -- of CR_1024x8
   30