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MROD_X_Out

Adr_Latch

Documentation for architecture MROD_X_Out/Adr_Latch/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'Adr_Latch'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   generic(
   10  --     Width :  positive := 11);
   11  --   port(
   12  --     AD_PHASE   : in     std_logic;
   13  --     Clk        : in     std_logic;
   14  --     DSB        : in     std_logic;
   15  --     LADI       : in     std_logic;
   16  --     LOC_A      : out    std_logic_vector(63 downto Width);
   17  --     LWORDin_n  : in     std_logic;
   18  --     LWORDout_n : out    std_logic;
   19  --     LocBg_n    : in     std_logic;
   20  --     Rst_n      : in     std_logic;
   21  --     VME_A      : in     std_logic_vector(31 downto 1);
   22  --     VME_D      : in     std_logic_vector(31 downto 0));
   23  -- 
   24  -- EASE/HDL end ----------------------------------------------------------------
   25  
   26  architecture a0 of Adr_Latch is
   27  begin
   28     Process(Clk, Rst_n)
   29     Begin
   30        If Rst_n = '0' Then
   31           LWORDout_n <= '1';
   32           LOC_A(63 Downto Width) <= (Others => '0');
   33        ElsIf Rising_Edge(Clk) Then
   34           --Flow Trough when LADI inactive
   35           If LADI = '0' Then
   36              LOC_A(31 Downto Width) <= VME_A(31 Downto Width);
   37              LWORDout_n <= LWORDin_n;
   38           End If;
   39  
   40           --Capture High order address lines in case of A64
   41           --This is during the Address BroadCast after either
   42           --one or both datastrobes are active (DSB) during
   43           --the very FIRST cycle of the transfer (the Address
   44           --Broadcast Cycle)
   45           If AD_PHASE = '1' And DSB = '1' And LocBg_n = '0' Then
   46              LOC_A(63 Downto 32) <= VME_D;
   47           End If;
   48        End If;
   49     End Process;
   50  end architecture a0 ; -- of Adr_Latch
   51