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MROD_X_Out

RegEn

Documentation for architecture MROD_X_Out/RegEn/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'RegEn'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   generic(
   10  --     n :  positive := 8);
   11  --   port(
   12  --     Clk   : in     std_logic;
   13  --     D     : in     std_logic_vector(n-1 downto 0);
   14  --     En_n  : in     std_logic;
   15  --     Q     : out    std_logic_vector(n-1 downto 0);
   16  --     Rst_n : in     std_logic);
   17  -- 
   18  -- EASE/HDL end ----------------------------------------------------------------
   19  
   20  architecture a0 of RegEn is
   21  
   22  BEGIN
   23     Process (Clk, Rst_n)
   24     Begin
   25        If Rst_n = '0' Then
   26           Q <= (others => '0');
   27        ElsIf Rising_Edge(Clk) Then
   28           If En_n = '0' Then
   29              Q <= D;
   30           End If;
   31        End If;    
   32     End Process;
   33  end architecture a0 ; -- of RegEn
   34