Back

Index

MROD_X_Out

InterFPGA_Link_Container

Documentation for architecture MROD_X_Out/InterFPGA_Link_Container/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- Architecture 'a0' of 'InterFPGA_Link_Container.
    3  --------------------------------------------------------------------------------
    4  -- Copy of the interface declaration of Entity 'InterFPGA_Link_Container' :
    5  -- 
    6  --   port(
    7  --     ConfigEnable   : in     std_logic;
    8  --     ConfigIn       : in     std_logic;
    9  --     ConfigOut      : out    std_logic;
   10  --     LoopBack       : in     std_logic_vector(1 downto 0);
   11  --     PowerDown      : in     std_logic;
   12  --     RXN            : in     std_logic;
   13  --     RXP            : in     std_logic;
   14  --     RefClk         : in     std_logic;
   15  --     RxBufStatus    : out    std_logic_vector(1 downto 0);
   16  --     RxCharIsComma  : out    std_logic_vector(1 downto 0);
   17  --     RxCharIsK      : out    std_logic_vector(1 downto 0);
   18  --     RxClkCorCnt    : out    std_logic_vector(2 downto 0);
   19  --     RxCommaDet     : out    std_logic;
   20  --     RxData         : out    std_logic_vector(15 downto 0);
   21  --     RxDispErr      : out    std_logic_vector(1 downto 0);
   22  --     RxLossOfSync   : out    std_logic_vector(1 downto 0);
   23  --     RxNotInTable   : out    std_logic_vector(1 downto 0);
   24  --     RxPolarity     : in     std_logic;
   25  --     RxRealign      : out    std_logic;
   26  --     RxRecClk       : out    std_logic;
   27  --     RxReset        : in     std_logic;
   28  --     RxRunDisp      : out    std_logic_vector(1 downto 0);
   29  --     RxUsrClk       : in     std_logic;
   30  --     RxUsrClk2      : in     std_logic;
   31  --     TXN            : out    std_logic;
   32  --     TXP            : out    std_logic;
   33  --     TxBufErr       : out    std_logic;
   34  --     TxBypass8B10B  : in     std_logic_vector(1 downto 0);
   35  --     TxCharDispMode : in     std_logic_vector(1 downto 0);
   36  --     TxCharDispVal  : in     std_logic_vector(1 downto 0);
   37  --     TxCharIsK      : in     std_logic_vector(1 downto 0);
   38  --     TxData         : in     std_logic_vector(15 downto 0);
   39  --     TxInhibit      : in     std_logic;
   40  --     TxKErr         : out    std_logic_vector(1 downto 0);
   41  --     TxPolarity     : in     std_logic;
   42  --     TxReset        : in     std_logic;
   43  --     TxRunDisp      : out    std_logic_vector(1 downto 0);
   44  --     TxUsrClk       : in     std_logic;
   45  --     TxUsrClk2      : in     std_logic);
   46  -- 
   47  -- EASE/HDL end ----------------------------------------------------------------
   48  
   49  architecture a0 of InterFPGA_Link_Container is
   50  
   51     Component MGT_InterFPGA is
   52        port (
   53           CONFIGENABLE : in std_logic;
   54           CONFIGIN : in std_logic;
   55           LOOPBACK_IN : in std_logic_vector (1 downto 0);
   56           POWERDOWN : in std_logic;
   57           REFCLK_IN : in std_logic;
   58           RXN : in std_logic;
   59           RXP : in std_logic;
   60           RXPOLARITY : in std_logic;
   61           RXRESET : in std_logic;
   62           RXUSRCLK : in std_logic;
   63           RXUSRCLK2 : in std_logic;
   64           TXBYPASS8B10B_IN : in std_logic_vector (1 downto 0);
   65           TXCHARDISPMODE_IN : in std_logic_vector (1 downto 0);
   66           TXCHARDISPVAL_IN : in std_logic_vector (1 downto 0);
   67           TXCHARISK_IN : in std_logic_vector (1 downto 0);
   68           TXDATA_IN : in std_logic_vector (15 downto 0);
   69           TXINHIBIT_IN : in std_logic;
   70           TXPOLARITY_IN : in std_logic;
   71           TXRESET_IN : in std_logic;
   72           TXUSRCLK : in std_logic;
   73           TXUSRCLK2 : in std_logic;
   74           CONFIGOUT : out std_logic;
   75           RXBUFSTATUS : out std_logic_vector (1 downto 0);
   76           RXCHARISCOMMA : out std_logic_vector (1 downto 0);
   77           RXCHARISK : out std_logic_vector (1 downto 0);
   78           RXCLKCORCNT : out std_logic_vector (2 downto 0);
   79           RXCOMMADET : out std_logic;
   80           RXDATA : out std_logic_vector (15 downto 0);
   81           RXDISPERR : out std_logic_vector (1 downto 0);
   82           RXLOSSOFSYNC : out std_logic_vector (1 downto 0);
   83           RXNOTINTABLE : out std_logic_vector (1 downto 0);
   84           RXREALIGN : out std_logic;
   85           RXRECCLK : out std_logic;
   86           RXRUNDISP : out std_logic_vector (1 downto 0);
   87           TXBUFERR_OUT : out std_logic;
   88           TXKERR_OUT : out std_logic_vector (1 downto 0);
   89           TXN_OUT : out std_logic;
   90           TXP_OUT : out std_logic;
   91           TXRUNDISP_OUT : out std_logic_vector (1 downto 0));
   92     End Component;
   93  
   94  begin
   95      U0: MGT_InterFPGA
   96           port map (
   97            CONFIGENABLE => Configenable,
   98            CONFIGIN => ConfigIn,
   99            LOOPBACK_IN => LoopBack,
  100            POWERDOWN => PowerDown,
  101            REFCLK_IN => RefClk,
  102            RXN => RXN,
  103            RXP => RXP,
  104            RXPOLARITY => RXPolarity,
  105            RXRESET => RXReset,
  106            RXUSRCLK => RXUsrClk,
  107            RXUSRCLK2 => RXUsrClk2,
  108            TXBYPASS8B10B_IN => TxByPass8B10B,
  109            TXCHARDISPMODE_IN => TxCharDispMode,
  110            TXCHARDISPVAL_IN => TxCharDispVal,
  111            TXCHARISK_IN => TxCharIsK,
  112            TXDATA_IN => TxData,
  113            TXINHIBIT_IN => TxInhibit,
  114            TXPOLARITY_IN => TxPolarity,
  115            TXRESET_IN => TxReset,
  116            TXUSRCLK => TXUsrClk,
  117            TXUSRCLK2 => TXUsrClk2,
  118            CONFIGOUT => ConfigOut,
  119            RXBUFSTATUS(1 downto 0) => RxBufStatus(1 downto 0),
  120            RXCHARISCOMMA(1 downto 0) => RXCharIsComma(1 downto 0),
  121            RXCHARISK(1 downto 0) => RXCharIsK(1 downto 0),
  122            RXCLKCORCNT(2 downto 0) => RxClkCorCnt(2 downto 0),
  123            RXCOMMADET => RxCommaDet,
  124            RXDATA(15 downto 0) => RxData(15 downto 0),
  125            RXDISPERR(1 downto 0) => RxDispErr(1 downto 0),
  126            RXLOSSOFSYNC(1 downto 0) => RxLossOfSync(1 downto 0),
  127            RXNOTINTABLE(1 downto 0) => RxNotInTable(1 downto 0),
  128            RXREALIGN => RxRealign,
  129            RXRECCLK => RxRecClk,
  130            RXRUNDISP(1 downto 0) => RxRunDisp(1 downto 0),
  131            TXBUFERR_OUT => TxBufErr,
  132            TXKERR_OUT => TxKErr,
  133            TXN_OUT => TXN,
  134            TXP_OUT => TXP,
  135            TXRUNDISP_OUT => TxRunDisp);   
  136  end architecture a0 ; -- of InterFPGA_Link_Container
  137  
  138