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MROD_X_Out

AlmostFullGen

Documentation for architecture MROD_X_Out/AlmostFullGen/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'AlmostFullGen'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   generic(
   10  --     FullThreshold :  positive := 128;
   11  --     n             :  positive := 8);
   12  --   port(
   13  --     AlmostFull : out    std_logic;
   14  --     UsedW      : in     std_logic_vector(n-1 downto 0));
   15  -- 
   16  -- EASE/HDL end ----------------------------------------------------------------
   17  
   18  architecture a0 of AlmostFullGen is
   19  
   20  begin
   21       AlmostFull <= '1' when (Unsigned(UsedW) >= FullThreshold ) else '0';
   22  end architecture a0 ; -- of AlmostFullGen
   23  
   24