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MROD_X_Out

Gen_IRQ2

Documentation for architecture MROD_X_Out/Gen_IRQ2/rtl

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'rtl' of entity 'Gen_IRQ2'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     IRQ2_n : out    std_logic;
   11  --     Reg3d  : in     std_logic_vector(31 downto 0));
   12  -- 
   13  -- EASE/HDL end ----------------------------------------------------------------
   14  
   15  architecture rtl of Gen_IRQ2 is
   16  
   17  begin
   18     IRQ2_n <= Not(Reg3d(0) Or Reg3d(1) Or Reg3d(8) Or Reg3d(9) Or Reg3d(12));
   19  end architecture rtl ; -- of Gen_IRQ2
   20  
   21