Generated by EASE/HDL for peterj on Mon Jul 02 10:55:29 2007

Documentation for architecture MROD_X_Out/OrG4/a0

Contents Side Data Generated HDL

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- Architecture 'a0' of 'OrG4.
    3  --------------------------------------------------------------------------------
    4  -- Copy of the interface declaration of Entity 'OrG4' :
    5  -- 
    6  --   port(
    7  --     A : in     std_logic;
    8  --     B : in     std_logic;
    9  --     C : in     std_logic;
   10  --     D : in     std_logic;
   11  --     O : out    std_logic);
   12  -- 
   13  -- EASE/HDL end ----------------------------------------------------------------
   14  
   15  architecture a0 of OrG4 is
   16  
   17  BEGIN
   18     O <= A Or B Or C Or D;
   19  end architecture a0 ; -- of OrG4
   20