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MROD_X_Out

TTC_Bus_Bit_Fifo

Documentation for architecture MROD_X_Out/TTC_Bus_Bit_Fifo/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'TTC_Bus_Bit_Fifo'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     D     : in     std_logic;
   11  --     Empty : out    std_logic;
   12  --     Full  : out    std_logic;
   13  --     Q     : out    std_logic;
   14  --     RdClk : in     std_logic;
   15  --     RdReq : in     std_logic;
   16  --     Rst_n : in     std_logic;
   17  --     WrClk : in     std_logic;
   18  --     WrReq : in     std_logic);
   19  -- 
   20  -- EASE/HDL end ----------------------------------------------------------------
   21  
   22  architecture a0 of TTC_Bus_Bit_Fifo is
   23  
   24    component fifo_15x1
   25      port (
   26      din: IN std_logic_VECTOR(0 downto 0);
   27      rd_clk: IN std_logic;
   28      rd_en: IN std_logic;
   29      rst: IN std_logic;
   30      wr_clk: IN std_logic;
   31      wr_en: IN std_logic;
   32      dout: OUT std_logic_VECTOR(0 downto 0);
   33      empty: OUT std_logic;
   34      full: OUT std_logic);
   35    end component;
   36  
   37    signal RstIntern: Std_Logic;
   38    signal Din: Std_Logic_VECTOR(0 downto 0);
   39    signal Dout: Std_Logic_VECTOR(0 downto 0);
   40  
   41  begin
   42  
   43     RstIntern <= Not Rst_n;
   44     Din(0) <= D;
   45     Q <= Dout (0);
   46  
   47     uc1: fifo_15x1
   48       port map(
   49           din => Din,
   50           rd_clk => RdClk,
   51           rd_en => RdReq,
   52           rst => RstIntern,
   53           wr_clk => WrClk,
   54           wr_en => WrReq,
   55           dout => Dout,
   56           empty => Empty,
   57           full => Full
   58       );
   59  
   60  end architecture a0 ; -- of TTC_Bus_Bit_Fifo
   61