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MROD_X_Out
FPGA| Generated by EASE/HDL for peterj on Mon Jul 02 10:55:26 2007 |
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MROD_X_Out |
FPGA |
| Contents | Side Data | Generated HDL |
1 -- EASE/HDL begin -------------------------------------------------------------- 2 -- 3 -- Architecture 'Structure' of entity 'FPGA'. 4 -- 5 -------------------------------------------------------------------------------- 6 -- 7 -- Copy of the interface declaration: 8 -- 9 -- generic( 10 -- MS1_Wait : natural := 1; 11 -- Date_ID : integer := 0; 12 -- Revision_ID : integer := 0; 13 -- MS2_Wait : natural := 1); 14 -- port( 15 -- AM : in std_logic_vector(5 downto 0); 16 -- AM10_Rst_n : out std_logic; 17 -- ASP_Con_n : in std_logic; 18 -- AS_n : in std_logic; 19 -- Ack : out std_logic; 20 -- BERR_n : out std_logic; 21 -- Busy_1A : in std_logic; 22 -- Busy_1B : in std_logic; 23 -- Busy_2A : in std_logic; 24 -- Busy_2B : in std_logic; 25 -- Busy_3A : in std_logic; 26 -- Busy_3B : in std_logic; 27 -- Busy_4A : in std_logic; 28 -- Busy_4B : in std_logic; 29 -- CSa_n : out std_logic; 30 -- CSb_n : out std_logic; 31 -- Clk : in std_logic; 32 -- Clkx2 : in std_logic; 33 -- DENIN0_n : out std_logic; 34 -- DENIN1_n : out std_logic; 35 -- DENO_n : out std_logic; 36 -- DMAR1_n : out std_logic; 37 -- DMAR2_n : out std_logic; 38 -- DS0_n : in std_logic; 39 -- DS1_n : in std_logic; 40 -- DS2401 : inout std_logic; 41 -- DTACK_OE_n : out std_logic; 42 -- DTACK_n : out std_logic; 43 -- FLAG0a : in std_logic; 44 -- FLAG0b : in std_logic; 45 -- FLAG1a : out std_logic; 46 -- FLAG1b : out std_logic; 47 -- FLAG2a : in std_logic; 48 -- FLAG2b : in std_logic; 49 -- FLAG3a : in std_logic; 50 -- FLAG3b : in std_logic; 51 -- GAP_n : in std_logic; 52 -- GA_n : in std_logic_vector(4 downto 0); 53 -- HBG_n : in std_logic; 54 -- HBR_n : out std_logic; 55 -- IACKIN_n : in std_logic; 56 -- IACKOUT_n : out std_logic; 57 -- IACK_n : in std_logic; 58 -- IRQ0a_n : out std_logic; 59 -- IRQ0b_n : out std_logic; 60 -- IRQ1a_n : out std_logic; 61 -- IRQ1b_n : out std_logic; 62 -- IRQ2a_n : out std_logic; 63 -- IRQ2b_n : out std_logic; 64 -- LDOWN_n : in std_logic; 65 -- LEAB_n : out std_logic; 66 -- LEDs : out std_logic_vector(3 downto 0); 67 -- LFF_n : in std_logic; 68 -- LHC_Clk : in std_logic; 69 -- LRL : in std_logic_vector(3 downto 0); 70 -- LWORD_n : in std_logic; 71 -- LocalBAR : in std_logic_vector(4 downto 0); 72 -- MS0_n : in std_logic; 73 -- MS1_n : in std_logic; 74 -- MS2_n : in std_logic; 75 -- MS3_n : in std_logic; 76 -- Module_En : out std_logic; 77 -- ROD_Busy : out std_logic; 78 -- RXN_1A : in std_logic; 79 -- RXN_1B : in std_logic; 80 -- RXN_2A : in std_logic; 81 -- RXN_2B : in std_logic; 82 -- RXN_3A : in std_logic; 83 -- RXN_3B : in std_logic; 84 -- RXN_4A : in std_logic; 85 -- RXN_4B : in std_logic; 86 -- RXP_1A : in std_logic; 87 -- RXP_1B : in std_logic; 88 -- RXP_2A : in std_logic; 89 -- RXP_2B : in std_logic; 90 -- RXP_3A : in std_logic; 91 -- RXP_3B : in std_logic; 92 -- RXP_4A : in std_logic; 93 -- RXP_4B : in std_logic; 94 -- R_W_n : out std_logic; 95 -- Redy_a : in std_logic; 96 -- Redy_b : in std_logic; 97 -- Rocket_XClk : in std_logic; 98 -- RstSharcC_n : out std_logic; 99 -- RstSharcD_n : out std_logic; 100 -- RstSharcE_n : out std_logic; 101 -- RstSharcF_n : out std_logic; 102 -- RstSharc_n : out std_logic; 103 -- Rst_n : in std_logic; 104 -- SDRAM_A : out std_logic_vector(12 downto 0); 105 -- SDRAM_BA : out std_logic_vector(1 downto 0); 106 -- SDRAM_CAS_n : out std_logic; 107 -- SDRAM_CKE : out std_logic; 108 -- SDRAM_CLK : out std_logic; 109 -- SDRAM_CLKin : in std_logic; 110 -- SDRAM_CS_n : out std_logic; 111 -- SDRAM_DQ : inout std_logic_vector(31 downto 0); 112 -- SDRAM_DQM : out std_logic_vector(3 downto 0); 113 -- SDRAM_RAS_n : out std_logic; 114 -- SDRAM_WE_n : out std_logic; 115 -- SLINK_CLK : out std_logic; 116 -- SLINK_CLKin : in std_logic; 117 -- SMBClk : out std_logic; 118 -- SMBData : inout std_logic; 119 -- SWDEN_n : out std_logic; 120 -- SYSFAIL_En : out std_logic; 121 -- SharcAdr : inout std_logic_vector(22 downto 0); 122 -- SharcRd_n : inout std_logic; 123 -- SharcWr_n : inout std_logic; 124 -- Spare_1A : in std_logic_vector(4 downto 0); 125 -- Spare_1B : in std_logic_vector(4 downto 0); 126 -- Spare_2A : in std_logic_vector(4 downto 0); 127 -- Spare_2B : in std_logic_vector(4 downto 0); 128 -- Spare_3A : in std_logic_vector(4 downto 0); 129 -- Spare_3B : in std_logic_vector(4 downto 0); 130 -- Spare_4A : in std_logic_vector(4 downto 0); 131 -- Spare_4B : in std_logic_vector(4 downto 0); 132 -- TTC_n : in std_logic_vector(7 downto 0); 133 -- TXN_1A : out std_logic; 134 -- TXN_1B : out std_logic; 135 -- TXN_2A : out std_logic; 136 -- TXN_2B : out std_logic; 137 -- TXN_3A : out std_logic; 138 -- TXN_3B : out std_logic; 139 -- TXN_4A : out std_logic; 140 -- TXN_4B : out std_logic; 141 -- TXP_1A : out std_logic; 142 -- TXP_1B : out std_logic; 143 -- TXP_2A : out std_logic; 144 -- TXP_2B : out std_logic; 145 -- TXP_3A : out std_logic; 146 -- TXP_3B : out std_logic; 147 -- TXP_4A : out std_logic; 148 -- TXP_4B : out std_logic; 149 -- T_Alert_n : in std_logic; 150 -- TestCon : out std_logic_vector(15 downto 0); 151 -- UCTRL_n : out std_logic; 152 -- UD : out std_logic_vector(31 downto 0); 153 -- URESET_n : out std_logic; 154 -- UTEST_n : out std_logic; 155 -- UWEN_n : out std_logic; 156 -- VME_A : in std_logic_vector(31 downto 1); 157 -- VME_D : inout std_logic_vector(31 downto 0); 158 -- VME_IRQ_n : out std_logic_vector(7 downto 1); 159 -- WRITE_n : in std_logic); 160 -- 161 -- EASE/HDL end ---------------------------------------------------------------- 162 163 architecture Structure of FPGA is 164 165 begin 166 167 end architecture Structure ; -- of FPGA 168 169