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MROD_X_Out

Unused

Documentation for architecture MROD_X_Out/Unused/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'Unused'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     FLAG0a      : in     std_logic;
   11  --     FLAG0b      : in     std_logic;
   12  --     FLAG2a      : in     std_logic;
   13  --     FLAG2b      : in     std_logic;
   14  --     FLAG3a      : in     std_logic;
   15  --     FLAG3b      : in     std_logic;
   16  --     MS2_n       : in     std_logic;
   17  --     Reg3Fd      : out    std_logic_vector(31 downto 0);
   18  --     SDRAM_A     : out    std_logic_vector(12 downto 0);
   19  --     SDRAM_BA    : out    std_logic_vector(1 downto 0);
   20  --     SDRAM_CAS_n : out    std_logic;
   21  --     SDRAM_CKE   : out    std_logic;
   22  --     SDRAM_CLK   : out    std_logic;
   23  --     SDRAM_CLKin : in     std_logic;
   24  --     SDRAM_CS_n  : out    std_logic;
   25  --     SDRAM_DQ    : inout  std_logic_vector(31 downto 0);
   26  --     SDRAM_DQM   : out    std_logic_vector(3 downto 0);
   27  --     SDRAM_RAS_n : out    std_logic;
   28  --     SDRAM_WE_n  : out    std_logic;
   29  --     SLINK_CLK   : out    std_logic;
   30  --     SLINK_CLKin : in     std_logic;
   31  --     Spare_1A    : in     std_logic_vector(4 downto 0);
   32  --     Spare_1B    : in     std_logic_vector(4 downto 0);
   33  --     Spare_2A    : in     std_logic_vector(4 downto 0);
   34  --     Spare_2B    : in     std_logic_vector(4 downto 0);
   35  --     Spare_3A    : in     std_logic_vector(4 downto 0);
   36  --     Spare_3B    : in     std_logic_vector(4 downto 0);
   37  --     Spare_4A    : in     std_logic_vector(4 downto 0);
   38  --     Spare_4B    : in     std_logic_vector(4 downto 0);
   39  --     TTC_n       : in     std_logic_vector(7 downto 0);
   40  --     TestCon     : out    std_logic_vector(15 downto 0));
   41  -- 
   42  -- EASE/HDL end ----------------------------------------------------------------
   43  
   44  architecture a0 of Unused is
   45  
   46  begin
   47  
   48     SDRAM_A <= (Others => '0');
   49     SDRAM_BA <= (Others => '0');
   50     SDRAM_CAS_n <= '1';
   51     SDRAM_CKE <= '0';
   52     SDRAM_CLK <= '0';
   53     SDRAM_CS_n <= '1';
   54     SDRAM_DQ <= (Others => '0');
   55     SDRAM_DQM <= (Others => '0');
   56     SDRAM_RAS_n <= '1';
   57     SDRAM_WE_n <= '1';
   58     SLINK_CLK <= '0';
   59     TestCon <= (Others => '0');
   60  
   61     -- Xilinx ISE software optimizes away unused inputs.
   62     -- There is no other alternative then to add dummy functionality
   63     -- to avoid MAP throwing away unused input pins
   64     -- See Xilinx "Case # 538535 preserve unused input pins"
   65     -- Thus, make it possible to readback these input pins in a dummy register
   66  
   67     Reg3Fd(4 downto 0) <= Spare_1A or Spare_2A or Spare_3A or Spare_4A
   68                        or Spare_1B or Spare_2B or Spare_3B or Spare_4B;
   69     Reg3Fd(15 downto 5) <= (others => '0');
   70     Reg3Fd(16) <= '0';   
   71     Reg3Fd(17) <= '0';   
   72     Reg3Fd(18) <= '0';   
   73     Reg3Fd(19) <= '0';   
   74     Reg3Fd(20) <= TTC_n(0) Or TTC_n(2) Or TTC_n(3) Or TTC_n(6) Or TTC_n(7);  
   75     Reg3Fd(21) <= '0';
   76     Reg3Fd(22) <= SDRAM_CLKin Or SLINK_CLKin;   
   77     Reg3Fd(23) <= '0';   
   78     Reg3Fd(24) <= Flag0A Or Flag2A Or Flag3A Or Flag0B Or Flag2B Or Flag3B;        
   79     Reg3Fd(25) <= MS2_n;   
   80     Reg3Fd(31 downto 26) <= (others => '0');
   81  
   82  end architecture a0 ; -- of Unused
   83  
   84