Generated by EASE/HDL for peterj on Mon Jul 02 10:55:26 2007

Documentation for architecture MROD_X_Out/D_TTC_Mux/a0

Contents Side Data Generated HDL

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'D_TTC_Mux'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     D_TTC      : out    std_logic_vector(31 downto 0);
   11  --     EV_BC      : in     std_logic_vector(43 downto 0);
   12  --     Low_High_n : in     std_logic;
   13  --     TT         : in     std_logic_vector(7 downto 0));
   14  -- 
   15  -- EASE/HDL end ----------------------------------------------------------------
   16  
   17  architecture a0 of D_TTC_Mux is
   18  -- Low:
   19  --       TTCdata(31-0)  is extended L1ID (8 bits) + L1ID (24 bits).
   20  -- High: 
   21  --       TTCdata(31-20) unused, reserved for Orbit counter (12 bits)
   22  --       TTCdata(19-12) is trigger type (8 bits)
   23  --       TTCdata(11-0) is bunch counter ID (12 bits)
   24  begin
   25     Process (EV_BC, TT, Low_High_n)
   26     Begin
   27        If Low_High_n = '1' Then
   28           D_TTC <= EV_BC(31 Downto 0);
   29        Else
   30           D_TTC(31 downto 20) <= (Others => '0');
   31           D_TTC(19 downto 12) <= TT;
   32           D_TTC(11 downto 0) <= EV_BC(43 Downto 32);
   33        End If;
   34     End Process;
   35  end architecture a0 ; -- of D_TTC_Mux
   36  
   37