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MROD_X_Out

Fifo16384w32

Documentation for architecture MROD_X_Out/Fifo16384w32/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'Fifo16384w32'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     Clk   : in     std_logic;
   11  --     Data  : in     std_logic_vector(31 downto 0);
   12  --     Empty : out    std_logic;
   13  --     Full  : out    std_logic;
   14  --     Q     : out    std_logic_vector(31 downto 0);
   15  --     RdReq : in     std_logic;
   16  --     Rst_n : in     std_logic;
   17  --     UsedW : out    std_logic_vector(13 downto 0);
   18  --     WrReq : in     std_logic);
   19  -- 
   20  -- EASE/HDL end ----------------------------------------------------------------
   21  
   22  architecture a0 of Fifo16384w32 is
   23  
   24    component scfifo_16384x32
   25      port (
   26      clk: IN std_logic;
   27      din: IN std_logic_VECTOR(31 downto 0);
   28      rd_en: IN std_logic;
   29      rst: IN std_logic;
   30      wr_en: IN std_logic;
   31      data_count: OUT std_logic_VECTOR(13 downto 0);
   32      dout: OUT std_logic_VECTOR(31 downto 0);
   33      empty: OUT std_logic;
   34      full: OUT std_logic);
   35    end component;
   36  
   37    signal Rst_Internal: std_logic;
   38     
   39  begin
   40     
   41    Rst_Internal <= not Rst_n;
   42        
   43    uc1: scfifo_16384x32
   44        port map (
   45           clk => Clk,
   46           din => Data,
   47           rd_en => RdReq,
   48           rst => Rst_Internal,
   49           wr_en => WrReq,
   50           data_count => UsedW,
   51           dout => Q,
   52           empty => Empty,
   53           full => Full
   54        );
   55  
   56  end architecture a0 ; -- of Fifo16384w32
   57  
   58