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MROD_X_Out

DS2401_Functionality

Documentation for architecture MROD_X_Out/DS2401_Functionality/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'DS2401_Functionality'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   generic(
   10  --     Family_ID :  String := "00";
   11  --     ID        :  String := "000000000000";
   12  --     CRC       :  String := "00");
   13  --   port(
   14  --     CRC_o       : out    std_logic_vector(7 downto 0);
   15  --     Command     : out    std_logic_vector(7 downto 0);
   16  --     Family_ID_o : out    std_logic_vector(7 downto 0);
   17  --     I           : in     std_logic;
   18  --     ID_o        : out    std_logic_vector(47 downto 0);
   19  --     O           : out    std_logic);
   20  -- 
   21  -- EASE/HDL end ----------------------------------------------------------------
   22  
   23  architecture a0 of DS2401_Functionality is
   24     Constant Trstl: Time := 480 us;  -- 480 us <= Trstl < infinity
   25     Constant Tpdh: Time := 60 us;    -- 15 us <= Tpdh < 60 us
   26     Constant Tpdl: Time := 60 us;    -- 60 us <= Tpdl < 240 us
   27     Constant Tsamping_window_start: Time := 15 us;    -- 15 us
   28     Constant Tsamping_window_end: Time := 60 us;    -- 60 us
   29     Constant Tsu: Time := 1 us;    -- Tsu < 1 us
   30     Constant Tlowr: Time := 15 us;    -- 1 us <= Tlowr <= 15 us
   31     Constant Trdv: Time := 15 us;    -- Trdv = 15 us
   32     Constant Trelease: Time := 0 us;    -- 0 us <= Trelease <= 45 us
   33  begin
   34     Process
   35        Variable FamID: std_logic_vector(7 downto 0);
   36        Variable DevID: std_logic_vector(47 downto 0);
   37        Variable CrcID: std_logic_vector(7 downto 0);
   38     Begin
   39  
   40        -- "Receive Reset Pulse"
   41        wait until I = '0';
   42        wait for Trstl;
   43        wait until rising_Edge(I);
   44        wait for Tpdh;
   45  
   46        -- "Transmit Presence Pulse"
   47        O <= '0';
   48        wait for Tpdl;
   49        O <= '1';
   50  
   51        -- "Receive 8-bit ROM Function Command (LSB first)"
   52        for x in 0 to 7 loop
   53           wait until I = '0' and I'Event;
   54           wait for Tsamping_window_start;
   55           wait for (Tsamping_window_end - Tsamping_window_start) /2;
   56           -- Take the sample
   57           If I = '0' Or I = 'L' Then
   58              Command(x) <= '0';
   59           ElsIf I = '1' Or I = 'H' Then
   60              Command (x) <= '1';
   61           Else
   62              Command (x) <= 'U';
   63           End If;         
   64        End Loop;
   65  
   66        FamID := HexToStdLogicVector(Family_ID,8);
   67        DevID := HexToStdLogicVector(ID,48);
   68        CrcID := HexToStdLogicVector(CRC,8);
   69  
   70        Family_ID_o <= FamID;
   71        ID_o <= DevID;
   72        CRC_o <= CrcID;
   73  
   74        -- "Send 8-bit Family ID (LSB first)"
   75        for x in 0 to 7 loop
   76           wait until I = '0' and I'Event;
   77           wait for Tsu;
   78           O <= FamID(x);
   79           wait for Trdv - Tsu;
   80           wait for Trelease;
   81           O <= '1';
   82        End Loop;
   83        
   84        -- "Send 48-bit Device ID (LSB first)"
   85        for x in 0 to 47 loop
   86           wait until I = '0' and I'Event;
   87           wait for Tsu;
   88           O <= DevID(x);
   89           wait for Trdv - Tsu;
   90           wait for Trelease;
   91           O <= '1';
   92        End Loop;
   93  
   94        -- "Send 8-bit CRC (LSB first)"
   95        for x in 0 to 7 loop
   96           wait until I = '0' and I'Event;
   97           wait for Tsu;
   98           O <= CrcID(x);
   99           wait for Trdv - Tsu;
  100           wait for Trelease;
  101           O <= '1';
  102        End Loop;
  103        
  104     End Process;
  105  end architecture a0 ; -- of DS2401_Functionality
  106  
  107