Generated by EASE/HDL for peterj on Mon Jul 02 11:00:52 2007
Back Index MROD_X_In InputPiece a0

Documentation for concurrent statement MROD_X_In/InputPiece/a0/VanwegeEase52R10Bug

Contents Side Data Generated HDL

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Concurrent Statement 'VanwegeEase52R10Bug' in architecture 'a0' of entity 'InputPiece'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface signals:
    8  -- 
    9  -- Reg1Fd_net : in     std_logic_Vector(EVID_Width-1 downto 0);
   10  -- D          : out    std_logic_Vector(29 downto 0);
   11  -- Q_Tetris   : in     std_logic_Vector(17 downto 0);
   12  -- 
   13  -- EASE/HDL end ----------------------------------------------------------------
   14     
   15  --
   16      D(17 downto 0) <= Q_Tetris;
   17      D(29 downto 18) <= Reg1Fd_net;
   18  --
   19