Generated by
EASE/HDL
for
peterj
on Mon Jul 02 11:00:56 2007
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MROD_X_In
Documentation for entity MROD_X_In/TTC_BusRcv
Contents
Side Data
Generated HDL
Architectures
Architecture:
a0
Component: u0:
Sync_TTC_Bit
: a0
Component: u1:
Reg
: a0
Component: u2:
Sync_TTC_Bit
: a0
Component: u3:
InvMultiple
: a0