Generated by
EASE/HDL
for
peterj
on Mon Jul 02 11:00:56 2007
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Index
MROD_X_In
Documentation for entity MROD_X_In/ZeroSuppressPipe
Contents
Side Data
Generated HDL
Architectures
Architecture:
a0
Component: u3:
AndG2
: a0
Component: u5:
AndG2
: a0
Component: u12:
OrG2
: a0
Component: u14:
AndG2
: a0
Component: u11:
AndInv
: a0
Component: u13:
WordCounter
: a0
Component: u19:
MTrailer_Mux
: a0
Component: u20:
Reg1
: a0
Component: u1:
Reg1
: a0
Component: u8:
Reg1
: a0
Component: u15:
Reg1
: a0
Component: u16:
Reg1
: a0
Component: u17:
Reg1
: a0
Component: u0:
Reg
: a0
Component: u2:
Reg
: a0
Component: u18:
Reg
: a0
Component: u21:
Reg
: a0
Component: u6:
Reg1
: a0
Component: u4:
Reg1
: a0
Component: u10:
Reg1
: a0
Component: u9:
Reg
: a0
Component: u22:
AndG2
: a0
Component: u23:
SpyCnt
: a0
Component: u24:
TDC_Limit_Cnt
: a0
Component: u26:
Reg1
: a0
Component: u27:
Reg1
: a0
Component: u28:
Low
: a0
Component: u29:
OrG5
: a0
Component: u30:
SpyCnt
: a0
Component: u31:
Reg1
: a0
Component: u32:
AndInv
: a0
Component: u34:
Reg1
: a0
Component: u35:
AndInv
: a0
Component: u33:
Reg
: a0
Component: u36:
Reg1
: a0
Component: u37:
Reg1
: a0
Component: u38:
AddValue
: a0
Component: u39:
Reg1En
: a0
Component: u40:
Inv1
: a0
Component: u41:
OrG2
: a0
Component: u42:
FullFlagMux
: a0
Component: u44:
AndG2
: a0
Component: u43:
AndInv
: a0
Component: u45:
WcntCheck
: a0
Component: u47:
Reg1
: a0
Component: u46:
AndG3
: a0
Component: u25:
OrG3
: a0
Component: u7:
AndG3
: a0