Generated by
EASE/HDL
for
peterj
on Mon Jul 02 11:00:50 2007
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Index
MROD_X_In
Documentation for entity MROD_X_In/BufferInterface
Contents
Side Data
Generated HDL
Architectures
Architecture:
a0
Component: u1:
Mux
: a0
Component: u2:
Phase
: a0
Component: u3:
Reg1
: a0
Component: u5:
Reg1
: a0
Component: u6:
Buffer_Cntrl
: a0
Component: u7:
Reg1Pst
: a0
Component: u8:
Reg1Pst
: a0
Component: u9:
Reg1
: a0
Component: u10:
Reg
: a0
Component: u11:
Reg
: a0
Component: u12:
Reg
: a0
Component: u13:
Reg1
: a0
Component: u14:
Reg1
: a0
Component: u16:
RegEn
: a0
Component: u17:
Inv1
: a0
Component: u20:
Reg
: a0
Component: u22:
Reg
: a0
Component: u23:
Tri_SepOe
: a0
Component: u26:
Reg1
: a0
Component: u27:
Sharc_Fpga_Mux
: a0
Component: u25:
AllowOther
: a0
Component: u0:
PhaseMuxReg
: a0
Component: u15:
Reg1Pst
: a0
Component: u18:
Reg1Pst
: a0
Component: u4:
Reg1Pst
: a0
Component: u19:
RegPst
: a0
Component: u21:
OneToN
: a0
Component: u24:
Low
: a0
Component: u28:
Low
: a0