Back

Index

GOL

FSMux

Documentation for architecture GOL/FSMux/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'FSMux'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     GTMode : in     std_logic_Vector(2 downto 0);
   11  --     MD     : out    std_logic_Vector(31 downto 0);
   12  --     Rst_n  : in     std_logic;
   13  --     SClk   : in     std_logic;
   14  --     WD     : in     std_logic_Vector(31 downto 0);
   15  --     WDEN   : in     std_logic;
   16  --     WF     : in     std_logic_Vector(31 downto 0);
   17  --     WFEN   : in     std_logic;
   18  --     WrMD   : out    std_logic);
   19  -- 
   20  -- EASE/HDL end ----------------------------------------------------------------
   21  
   22  architecture a0 of FSMux is
   23  
   24    signal Fdata      : std_logic_vector(31 downto 0);
   25    signal Fwrite     : std_logic;
   26  
   27    --GTMode(0) : 1/0 : enable / disable CSM testrun
   28    --GTMode(1) : 1/0 : circulate fifo / fill fifo from SHARC (replace BOT+EOT)
   29    --GTMode(2) : 1/0 : triggered / untriggered test mode
   30  
   31  begin
   32  
   33    with GTMode(1) select Fdata <=        -- GTMode: circulate/fill (1/0)
   34      WD(31 downto 0) when '0',           -- fill fifo from sharc
   35      WF(31 downto 0) when others;        -- circulate fifo
   36  
   37    with GTMode(1) select Fwrite <=       -- GTMode: circulate/fill (1/0)
   38      WDEN when '0',                      -- fill fifo from sharc
   39      WFEN when others;                   -- circulate fifo
   40  
   41    ------------------------------------------------------------------------------
   42  
   43    -- store the multiplexed data
   44    
   45    pr1:
   46    process (SClk, Rst_n)
   47    begin
   48      if (Rst_n = '0') then
   49        WrMD <= '0';
   50        MD   <= (others => '0');
   51      elsif (rising_edge(SClk)) then
   52        WrMD <= Fwrite;
   53        if (Fwrite = '1') then
   54          MD <= Fdata;
   55        end if;
   56      end if;
   57    end process;
   58  
   59  end architecture a0 ; -- of FSMux
   60  
   61