Generated by EASE/HDL for peterj on Mon Jul 02 11:00:49 2007 |
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Contents | Side Data | Generated HDL |
1 -- EASE/HDL begin -------------------------------------------------------------- 2 -- 3 -- Architecture 'a0' of entity 'RegSharc'. 4 -- 5 -------------------------------------------------------------------------------- 6 -- 7 -- Copy of the interface declaration: 8 -- 9 -- port( 10 -- Data : in std_logic_Vector(31 downto 0); 11 -- Rst_n : in std_logic; 12 -- SClk : in std_logic; 13 -- Sel_n : in std_logic; 14 -- WD : out std_logic_Vector(31 downto 0); 15 -- WDEN : out std_logic; 16 -- Wr_n : in std_logic); 17 -- 18 -- EASE/HDL end ---------------------------------------------------------------- 19 20 architecture a0 of RegSharc is 21 22 signal QA, QB : std_logic; 23 signal WrPulse : std_logic; 24 25 begin 26 27 -- Sel_n and Wr_n must be low to generate a write pulse for the register. 28 -- The write pulse (1 clk period) occurs on the leading (falling) edge 29 -- of the (Sel_N and Wr_n) signal. 30 -- SHARC Watch out: This only works when Wr_n and/of Sel_n is de-asserted 31 -- at each new write cycle. This means that the SHARC must add a Hold Cycle 32 -- to ensure that Wr_n is de-asserted. 33 -- When a write cycle is started, there is one pulse coming on the rising 34 -- edge of the clock after the write action (Wr_n adn Sel_n) was initiated. 35 36 WrPulse <= QB and not QA; 37 38 pr1: 39 process (SClk, Rst_n) 40 begin 41 if (Rst_n = '0') then 42 QA <= '0'; 43 QB <= '0'; 44 elsif (rising_edge(SClk)) then 45 QA <= Sel_n or Wr_n; -- active low and function ! 46 QB <= QA; 47 end if; 48 end process; 49 50 pr2: 51 process (SClk, Rst_n) 52 begin 53 if (Rst_n = '0') then 54 WDEN <= '0'; 55 elsif (rising_edge(SClk)) then 56 WDEN <= WrPulse; -- delay by one cycle for fifo 57 end if; 58 end process; 59 60 prReg: 61 process (SClk, Rst_n) 62 begin 63 if (Rst_n = '0') then 64 WD <= (others => '0'); 65 elsif (rising_edge(SClk)) then 66 if (WrPulse = '1') then 67 WD <= Data; 68 end if; 69 end if; 70 end process; 71 72 end architecture a0 ; -- of RegSharc 73 74