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ZBase

RegFV

Documentation for architecture ZBase/RegFV/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'RegFV'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   generic(
   10  --     n :  positive := 8);
   11  --   port(
   12  --     Clk   : in     std_logic;
   13  --     D     : in     std_logic_Vector(n-1 downto 0);
   14  --     E_n   : in     std_logic;
   15  --     Q     : out    std_logic_Vector(n-1 downto 0);
   16  --     Rst_n : in     std_logic);
   17  -- 
   18  -- EASE/HDL end ----------------------------------------------------------------
   19  
   20  architecture a0 of RegFV is
   21  
   22  begin
   23  
   24    -- Register with Enable-low.
   25    -- Use as Freeze register (freeze when E_n = '0')
   26  
   27    pr0:
   28    process (Clk, Rst_n)
   29    begin
   30      if (Rst_n = '0') then
   31        Q <= (others => '0');
   32      elsif (rising_edge(Clk)) then
   33        if (E_n = '0') then
   34          Q <= D;
   35        end if;
   36      end if;    
   37    end process;
   38  
   39  end architecture a0 ; -- of RegFV
   40  
   41