Back

Index

GOL

EvtMux

Documentation for architecture GOL/EvtMux/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'EvtMux'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     DS         : out    std_logic_Vector(31 downto 0);
   11  --     ECR        : in     std_logic;
   12  --     EmptyB     : in     std_logic;
   13  --     EndEvt     : out    std_logic;
   14  --     Even_Odd_n : in     std_logic;
   15  --     ForceIdle  : in     std_logic;
   16  --     FullS      : in     std_logic;
   17  --     GTMode     : in     std_logic_Vector(2 downto 0);
   18  --     RdReq      : out    std_logic;
   19  --     Rst_n      : in     std_logic;
   20  --     SClk       : in     std_logic;
   21  --     WF         : in     std_logic_Vector(31 downto 0);
   22  --     WrDS       : out    std_logic);
   23  -- 
   24  -- EASE/HDL end ----------------------------------------------------------------
   25  
   26  architecture a0 of EvtMux is
   27  
   28    signal RdReqB     : std_logic;
   29    signal FEN        : std_logic;
   30    signal EndEvtInt  : std_logic;
   31    signal BOTEvt     : std_logic;
   32    signal EOTEvt     : std_logic;
   33    signal Hpar       : std_logic;
   34    signal ECnt       : std_logic_vector(11 downto 0);
   35    signal HeadTrail  : std_logic_vector( 1 downto 0);
   36    signal Fdata      : std_logic_vector(31 downto 0);
   37    --
   38    constant ID_SEP   : std_logic_vector(3 downto 0) :=   "1101"; -- Separator
   39    constant ID_EOE   : std_logic_vector(5 downto 0) := "001110"; -- End of Event !
   40    constant ID_BOT   : std_logic_vector(2 downto 0) :=    "101"; -- BOT identifier
   41    constant ID_EOT   : std_logic_vector(3 downto 0) :=   "1100"; -- EOT identifier
   42  
   43    --GTMode(0) : 1/0 : enable / disable CSM testrun
   44    --GTMode(1) : 1/0 : circulate fifo / fill fifo from SHARC (replace BOT+EOT)
   45    --GTMode(2) : 1/0 : triggered / untriggered test mode
   46  
   47  begin
   48  
   49    EndEvt <= EndEvtInt;
   50    RdReq  <= RdReqB;
   51  
   52    -- read FifoBuffer when (not EmptyBuffer and not FullSender and not ForceIdle)
   53    RdReqB <= '1' when (EmptyB = '0' and FullS = '0' and EndEvtInt = '0' and ForceIdle = '0') else '0';
   54  
   55    -- For the circulating data: look for BOT and EOT and EndOfEvent.
   56    -- When BOT or EOT found: replace eventcounter value by internal event counter.
   57    -- When EndOfEvent found: increment internal event counter.
   58    -- Ignore parity when checking for End of Event (xD0E).
   59  
   60    BOTEvt    <= '1' when (FEN = '1' and WF(31 downto 29) = ID_BOT) else '0'; -- Begin TDC
   61    EOTEvt    <= '1' when (FEN = '1' and WF(31 downto 28) = ID_EOT) else '0'; -- End TDC
   62    EndEvtInt <= '1' when (FEN = '1' and WF(31 downto 28) = ID_SEP
   63                                     and WF(25 downto 20) = ID_EOE) else '0'; -- End of Event
   64  
   65    -- Select ECnt to overwrite parts of the BOT and EOT words in the data.
   66  
   67    Headtrail <= (BOTEvt & EOTEvt) when (GTMode(1) = '1') else "00";
   68    with HeadTrail select Fdata <=
   69      WF(31 downto 27) & '0' & WF(25) & WF(24) & ECnt & WF(11 downto 0) when "10", -- BOT
   70      WF(31 downto 27) & '0' & WF(25) & WF(24) & ECnt & WF(11 downto 0) when "01", -- EOT
   71      WF(31 downto 27) & '0' & WF(25 downto 0) when others;   -- any other data unchanged
   72  
   73    ------------------------------------------------------------------------------
   74    
   75    prReq:
   76    process (SClk, Rst_n)
   77    begin
   78      if (Rst_n = '0') then
   79        FEN  <= '0';
   80        WrDS <= '0';
   81      elsif (rising_edge(SClk)) then
   82        -- WF (FData) and FEN  change  after the same clock edge.
   83        -- DS         and WrDS change  after the next clock edge.
   84        FEN  <= RdReqB;
   85        WrDS <= FEN;
   86      end if;
   87    end process;
   88  
   89    prBuf:
   90    process (SClk, Rst_n)
   91    begin
   92      if (Rst_n = '0') then
   93        DS <= (others => '0');
   94      elsif (rising_edge(SClk)) then
   95        if (FEN = '1') then
   96          DS <= Fdata(31 downto 27) & Hpar & Fdata(25 downto 0);
   97        end if;
   98      end if;
   99    end process;
  100  
  101    prCnt:
  102    process (SClk, Rst_n)
  103      variable cnt : unsigned(11 downto 0);
  104    begin
  105      if (Rst_n = '0') then
  106        cnt := (others => '0');
  107      elsif (rising_edge(SClk)) then
  108        if (GTMode(2 downto 0) = "000" or ECR = '1') then
  109          cnt := (others => '0');
  110        elsif (EndEvtInt = '1') then
  111          cnt := cnt + 1;
  112        end if;
  113      end if;
  114      ECnt <= std_logic_vector(cnt);
  115    end process;
  116  
  117    -- bit27 is the TDC serial parity error: should be 0, but leave as it is!
  118    -- bit26 is the GOL parity: should be calculated before sending the data.
  119    -- The outgoing MD (muxtiplexed data) gets new parity:
  120    -- The parity is calculated over 32 bits and inserted into bit 26.
  121    -- Note that bit Fdata(26) is "preset" zero before the calculation.
  122    -- Even_Odd_n selects whether the total parity is even or odd.
  123    --
  124  
  125    prPar:
  126    process (Fdata, Even_Odd_n)
  127      variable par : std_logic;
  128    begin
  129      par := not Even_Odd_n;       -- Even_Odd_n=0: use odd parity
  130      for i in 31 downto 0 loop
  131        par := par xor Fdata(i);
  132      end loop;
  133      Hpar <= par;
  134    end process;
  135  
  136  end architecture a0 ; -- of EvtMux
  137  
  138