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GOLSndWords

Documentation for architecture GOL/GOLSndWords/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'GOLSndWords'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     CAV   : out    std_logic;
   11  --     DAV   : out    std_logic;
   12  --     Data  : out    std_logic_Vector(31 downto 0);
   13  --     EAV   : out    std_logic;
   14  --     EnSD  : in     std_logic;
   15  --     LWD   : in     std_logic_Vector(31 downto 0);
   16  --     RqD   : out    std_logic;
   17  --     Rst_n : in     std_logic;
   18  --     WDE   : in     std_logic;
   19  --     XClk  : in     std_logic);
   20  -- 
   21  -- EASE/HDL end ----------------------------------------------------------------
   22  
   23  architecture a0 of GOLSndWords is
   24  
   25    type states is (doIdle1, doIdle2, doData);
   26    signal state  : states;
   27    signal RqData : std_logic;
   28    signal Toggle : std_logic;
   29    signal Cycle  : unsigned (6 downto 0);
   30    signal ForceIdle : std_logic;
   31  
   32  begin
   33  
   34    Data <= LWD;
   35    EAV  <= Toggle;
   36  
   37    RqData <= '1' when (WDE = '0' and EnSD = '1') else '0';   -- when D fifo not empty
   38  
   39    ForceIdle <= '1' when (Cycle(4 downto 0) = 31) else '0';
   40    --ForceIdle <= '1' when (Cycle(3 downto 0) = 15) else '0';
   41  
   42    prTrx:
   43    process (XClk, Rst_n)
   44    begin
   45      if (Rst_n = '0') then
   46        Toggle <= '0';
   47        CAV  <= '0';                      --
   48        DAV  <= '0';                      -- idle
   49        RqD  <= '0';                      -- Request no Data
   50        state  <= doIdle1;
   51        Cycle  <= (others => '0');
   52      elsif (rising_edge(XClk)) then
   53        if (Toggle = '1') then
   54          Toggle <= '0';
   55          case state is
   56          when doIdle1 =>
   57            CAV  <= '0';                  --
   58            DAV  <= '0';                  -- idle
   59            RqD  <= '0';                  -- Request no Data
   60            state <= doIdle2;
   61          when doIdle2 =>
   62            CAV  <= '0';                  --
   63            DAV  <= '0';                  -- idle
   64            if (RqData = '1') then
   65              RqD   <= '1';               -- Request Data
   66              state <= doData;
   67            else
   68              RqD   <= '0';               -- Request no Data
   69              state <= doIdle1;
   70            end if;
   71          when doData =>
   72            CAV  <= '0';                  --
   73            DAV  <= '1';                  -- normal data
   74            Cycle <= Cycle + 1;
   75            if (ForceIdle = '1') then
   76              RqD   <= '0';               -- Request no Data
   77              state <= doIdle1;
   78            elsif (RqData = '1') then
   79              RqD   <= '1';               -- Request Data
   80              state <= doData;
   81            else
   82              RqD   <= '0';               -- Request no Data
   83              state <= doIdle1;
   84            end if;
   85          when others =>
   86            CAV  <= '0';                  --
   87            DAV  <= '0';                  -- idle
   88            RqD  <= '0';                  -- Request no Data
   89            state <= doIdle1;
   90          end case;
   91        else
   92          RqD    <= '0';                  -- Request no Data
   93          Toggle <= '1';
   94        end if;
   95      end if;
   96    end process;
   97  
   98  end architecture a0 ; -- of GOLSndWords
   99  
  100