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MGTR

ResetSeq

Documentation for architecture MGTR/ResetSeq/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- Architecture 'a0' of 'ResetSeq.
    3  --------------------------------------------------------------------------------
    4  -- Copy of the interface declaration of Entity 'ResetSeq' :
    5  -- 
    6  --   port(
    7  --     Clk      : in     std_logic;
    8  --     DRst     : out    std_logic;
    9  --     Lock     : in     std_logic;
   10  --     Reset_n  : in     std_logic;
   11  --     RstSw_n  : in     std_logic;
   12  --     Rst_n    : out    std_logic;
   13  --     RxRst    : out    std_logic;
   14  --     TickUS   : out    std_logic;
   15  --     TxRst    : out    std_logic;
   16  --     XClk     : in     std_logic;
   17  --     doDRst_n : in     std_logic);
   18  -- 
   19  -- EASE/HDL end ----------------------------------------------------------------
   20  
   21  architecture a0 of ResetSeq is
   22  
   23    signal LTickUs    : std_logic;
   24    signal LockEnd    : std_logic;
   25    signal PwClear_n  : std_logic;
   26    signal RstPhase   : std_logic_vector(3 downto 0);
   27  
   28    constant NTPUS  : unsigned(5 downto 0) := "100000";   --   33 ticks per us.
   29  
   30  begin
   31  
   32    TickUS <= LTickUs;                    -- 1 tick wide pulse every microsecond
   33    DRst   <= not RstPhase(0);            -- inactive at t= 1 us
   34    TxRst  <= not RstPhase(1);            -- inactive at t= 2 us
   35    RxRst  <= not RstPhase(2);            -- inactive at t= 3 us
   36    Rst_n  <=     RstPhase(3);            -- inactive at t= 4 us
   37  
   38    ------------------------------------------------------------------------
   39  
   40    pr1:
   41    process (Clk, Reset_n)
   42      variable cntbase : unsigned (5 downto 0);
   43    begin
   44      if (Reset_n = '0') then             -- only on power-up reset !
   45        PwClear_n <= '0';                 -- assert powerclear (low)
   46        LTickUs <= '0';
   47        cntbase := (others => '0');
   48        --cntbase := '0' & NTPUS(5 downto 1);   -- halfway ...
   49      elsif (rising_edge(Clk)) then
   50        if (cntbase = NTPUS) then         -- 33 clockticks per us.
   51          PwClear_n <= '1';               -- deassert powerclear after 1 us.
   52          LTickUs <= '1';                 -- active high pulse (tw=30 ns) every 1 us.
   53          cntbase := (others => '0');
   54        else
   55          LTickUs <= '0';
   56          cntbase := cntbase + 1;
   57        end if;
   58      end if;
   59    end process;
   60  
   61    ---------------------------------------------------------------------------
   62  
   63    -- The following processes work on Power-Up reset and also when
   64    -- the RstSw_n signal is asserted via external pin (switch).
   65  
   66  
   67    pr3:
   68    process (Clk, RstSw_n)
   69    begin
   70      if (RstSw_n = '0') then             -- on power-up reset or switch reset
   71        LockEnd <= '0';
   72      elsif (rising_edge(Clk)) then
   73        if (LTickUs = '1') then
   74          if (Lock = '1') then            -- if (Lock = '1' or CntUs = 200) then
   75            LockEnd <= '1';
   76          end if;
   77        end if;
   78      end if;
   79    end process;
   80  
   81    pr4:
   82    process (Clk, RstSw_n, doDrst_n)
   83    begin
   84      if (RstSw_n = '0') then                     -- on power-up or switch reset
   85        RstPhase <= "000" & doDrst_n;             -- do DCM reset when doDrst_n='0' 
   86      elsif (rising_edge(Clk)) then
   87        if (LTickUs = '1' and PwClear_n = '1') then
   88          RstPhase(0) <= '1';
   89          if (LockEnd = '1') then         --if (LockEnd = '1' or Lock = '1') then
   90            RstPhase(3 downto 1) <= RstPhase(2 downto 0);
   91          end if;
   92        end if;
   93      end if;
   94    end process;
   95  
   96  --  pr5:                                  -- cross the border from SClk to XClk
   97  --  process (XClk, PwClear_n, RstSw_n)
   98  --    variable synca,syncb : std_logic_vector (1 downto 0);
   99  --  begin
  100  --    if (RstSw_n = '0') then              -- on power-up or switch reset
  101  --      synca := "11";
  102  --      syncb := "11";
  103  --    elsif (rising_edge(XClk)) then
  104  --      syncb    := synca;                -- second stage
  105  --      synca(0) := not RstPhase(1);      -- first stage
  106  --      synca(1) := not RstPhase(2);
  107  --    end if;
  108  --    TxRst  <= syncb(0);                 -- inactive at t= 2 us
  109  --    RxRst  <= syncb(1);                 -- inactive at t= 3 us
  110  --  end process;
  111  
  112  end architecture a0 ; -- of ResetSeq
  113  
  114