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MROD_X_In

WcntCheck

Documentation for architecture MROD_X_In/WcntCheck/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'WcntCheck'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     Clear       : in     std_logic;
   11  --     Clk         : in     std_logic;
   12  --     EnaComp     : in     std_logic;
   13  --     EotWcnt     : in     std_logic_Vector(31 downto 0);
   14  --     Equal       : out    std_logic;
   15  --     Inc         : in     std_logic;
   16  --     No_Override : in     std_logic;
   17  --     Rst_n       : in     std_logic);
   18  -- 
   19  -- EASE/HDL end ----------------------------------------------------------------
   20  
   21  architecture a0 of WcntCheck is
   22  
   23    signal MyWcnt   : std_logic_vector(11 downto 0);
   24  
   25  begin
   26  
   27    prcompare:
   28    process (Clk, Rst_n)
   29    begin
   30      if (Rst_n = '0') then
   31        Equal <= '0';
   32      elsif (rising_edge(Clk)) then
   33        if (EnaComp = '1' and No_Override = '1' and EotWcnt(11 downto 0) = MyWcnt) then
   34          Equal <= '1';
   35        else
   36          Equal <= '0';
   37        end if;
   38      end if;
   39    end process;
   40  
   41    -- The Inc signal is also present when the Clear signals comes.
   42    -- During simulation I see delta-delay differences between the Clear and Inc
   43    -- signals, therefore I can not use a simple if-then-else syntax.
   44  
   45    prcount:
   46    process (Clk, Rst_n)
   47      variable Cnt: unsigned(11 downto 0);
   48    begin
   49      if (Rst_n = '0') then
   50        Cnt := (others => '0');
   51      elsif (rising_edge(Clk)) then
   52        if (Inc = '1') then
   53          if (Clear = '1') then
   54            Cnt := x"002";
   55          else
   56            Cnt := Cnt + 1;
   57          end if;
   58        end if;
   59      end if;
   60      MyWcnt <= std_logic_vector(Cnt);
   61    end process;
   62  
   63  end architecture a0 ; -- of WcntCheck
   64  
   65