Documentation for architecture GOL/TrigCnt/a0
VHDL Contents
1 architecture a0 of TrigCnt is
21
22 signal TCnt : std_logic_vector(7 downto 0) ;
23 signal Busy : std_logic ;
24 signal CntFull : std_logic ;
25 signal CntLast : std_logic ;
26 signal IdleRMode : std_logic;
27 signal EventDone : std_logic;
28
29 begin
34
35 ForceIdle <= '1' when (IdleRMode = '1' and EventDone = '1') else '0';
40
41 Busy <= '1' when (TCnt /= "00000000") else '0';
42 CntFull <= '1' when (TCnt = "11111111") else '0';
43 CntLast <= '1' when (TCnt = "00000001") else '0';
44
45 prCnt:
46 process (SClk, Rst_n, ECR)
47 variable count: unsigned(7 downto 0);
48 begin
49 if (Rst_n = '0' or ECR = '1') then
50 IdleRMode <= '1'; EventDone <= '1'; count := (others => '0'); elsif (rising_edge(SClk)) then
54 case GTMode is
55 when "000" =>
56 EventDone <= '1'; IdleRMode <= '1'; when "001" | "011" =>
59 EventDone <= '0'; IdleRMode <= '0'; when "110" | "010" =>
62 if (EndEvt = '1') then
64 EventDone <= '1'; count := (others => '0');
66 end if;
67 IdleRMode <= '1'; when "111" =>
69 if (Trigger = '1' and EndEvt = '1') then
70 null;
71 elsif (Trigger = '1') then
72 if (CntFull = '0') then
73 count := count + 1;
74 end if;
75 elsif (EndEvt = '1') then
76 if (Busy = '1') then
77 count := count - 1;
78 end if;
79 end if;
80 if (EndEvt = '1' and Busy = '1' and CntLast = '1') then
81 IdleRMode <= '1'; EventDone <= '1'; else
84 IdleRMode <= not Busy; EventDone <= not Busy; end if;
87 when others =>
88 IdleRMode <= '1'; EventDone <= '1'; end case;
92 end if;
93 TCnt <= std_logic_vector(count);
94 end process;
95
96 end architecture a0 ;