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ZBase

RegF

Documentation for architecture ZBase/RegF/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'RegF'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     Clk   : in     std_logic;
   11  --     D     : in     std_logic;
   12  --     E_n   : in     std_logic;
   13  --     Q     : out    std_logic;
   14  --     Rst_n : in     std_logic);
   15  -- 
   16  -- EASE/HDL end ----------------------------------------------------------------
   17  
   18  architecture a0 of RegF is
   19  
   20    -- Register with Enable-low.
   21    -- Use as Freeze register (freeze when E_n = '0')
   22  
   23  begin
   24  
   25    pr0:
   26    process (Clk, Rst_n)
   27    begin
   28      if (Rst_n = '0') then
   29        Q <= '0';
   30      elsif (rising_edge(Clk)) then
   31        if (E_n = '0') then
   32          Q <= D;
   33        end if;
   34      end if;    
   35    end process;
   36  
   37  end architecture a0 ; -- of RegF
   38  
   39