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MGTR

TxEncode

Documentation for architecture MGTR/TxEncode/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'TxEncode'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     CAV       : in     std_logic;
   11  --     DAV       : in     std_logic;
   12  --     Data      : in     std_logic_Vector(31 downto 0);
   13  --     EAV       : in     std_logic;
   14  --     Rst_n     : in     std_logic;
   15  --     TxCharIsK : out    std_logic_Vector(1 downto 0);
   16  --     TxData    : out    std_logic_Vector(15 downto 0);
   17  --     XClk      : in     std_logic);
   18  -- 
   19  -- EASE/HDL end ----------------------------------------------------------------
   20  
   21  architecture a0 of TxEncode is
   22  
   23    --MGT IDLE              = <K28.5>,<D16.2>
   24    constant IDLE_Data    : std_logic_vector(15 downto 0) := x"BC50";
   25    constant IDLE_K       : std_logic_vector( 1 downto 0) := "10";
   26    --MGT Carrier Extend    = <K23.7>,<K23.7>
   27    constant CarExt_Data  : std_logic_vector(15 downto 0) := x"F7F7";
   28    constant CarExt_K     : std_logic_vector( 1 downto 0) := "11";
   29    --MGT Error Propagation = <K30.7>,<K30.7>
   30    constant ErrProp_Data : std_logic_vector(15 downto 0) := x"FEFE";
   31    constant ErrProp_K    : std_logic_vector( 1 downto 0) := "11";
   32    constant DATA_K       : std_logic_vector( 1 downto 0) := "00";
   33    --
   34    constant plain        : std_logic := '0';
   35    signal   TsData       : std_logic_vector(15 downto 0);
   36  
   37  begin
   38  
   39    pr1:
   40    process (XClk, Rst_n)
   41    begin
   42      if (Rst_n = '0') then
   43        TxData    <= IDLE_Data;
   44        TsData    <= (others => '0');
   45        TXCharIsK <= IDLE_K;
   46      elsif (rising_edge(XClk)) then
   47        if (CAV = '0' and DAV = '0') then
   48          TxData    <= IDLE_Data;
   49          TXCharIsK <= IDLE_K;
   50        elsif (CAV = '0' and DAV = '1') then             
   51          if (plain = '1') then
   52            -- The Xilinx MGT model sends its data in the order
   53            -- din<31:24>, din<23:16>, din<15:8>, din<7:0>.
   54            -- The correct word order is selected by EAV (no byte remapping).
   55            -- dout0(15 downto  0) <= din(31 downto 16);
   56            -- dout1(15 downto  0) <= din(15 downto 0);
   57            if (EAV = '0') then
   58              TsData(15 downto  0) <= Data(15 downto 0);
   59              TxData(15 downto  0) <= Data(31 downto 16);
   60            else
   61              TxData(15 downto  0) <= TsData(15 downto 0);
   62            end if;
   63          else
   64            -- The GOL sends its data in the following order
   65            -- din<7:0>, din<15:8>, din<23:16>, din<31:24>.
   66            -- Thus remap the databus so the byte order is swapped:
   67            -- dout0(15 downto  0) <= din( 7 downto  0),din(15 downto  8);
   68            -- dout1(15 downto  0) <= din(23 downto 16),din(31 downto 24);
   69            if (EAV = '0') then
   70              TsData(15 downto  0) <= Data(31 downto 16);
   71              TxData(15 downto  0) <= Data(7 downto 0)   & Data(15 downto 8);
   72            else
   73              TxData(15 downto  0) <= TsData(7 downto 0) & TsData(15 downto 8);
   74            end if;
   75          end if;
   76          TXCharIsK <= DATA_K;
   77        elsif (CAV = '1' and DAV = '0') then             
   78          TxData    <= CarExt_Data;
   79          TXCharIsK <= CarExt_K;
   80        else
   81          TxData    <= ErrProp_Data;
   82          TXCharIsK <= ErrProp_K;
   83        end if;
   84      end if;
   85    end process;
   86  
   87  end architecture a0 ; -- of TxEncode
   88  
   89