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MGTR

FIFO15w

Documentation for architecture MGTR/FIFO15w/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'FIFO15w'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     AFull : out    std_logic;
   11  --     D     : in     std_logic_Vector(31 downto 0);
   12  --     Empty : out    std_logic;
   13  --     HFull : out    std_logic;
   14  --     Q     : out    std_logic_Vector(31 downto 0);
   15  --     RClk  : in     std_logic;
   16  --     RdReq : in     std_logic;
   17  --     Rst_n : in     std_logic;
   18  --     WClk  : in     std_logic;
   19  --     WrReq : in     std_logic);
   20  -- 
   21  -- EASE/HDL end ----------------------------------------------------------------
   22  
   23  architecture a0 of FIFO15w is
   24  
   25  -- This entity and architecture make a wrapper around the fifo15w32 component.
   26  -- (The component was generated with Xilinx Core Generator.)
   27  
   28    component fifo15w32
   29      port (
   30        din: IN std_logic_vector(31 downto 0);
   31        wr_en: IN std_logic;
   32        wr_clk: IN std_logic;
   33        rd_en: IN std_logic;
   34        rd_clk: IN std_logic;
   35        rst: IN std_logic;
   36        dout: OUT std_logic_vector(31 downto 0);
   37        full: OUT std_logic;
   38        empty: OUT std_logic;
   39        almost_full: OUT std_logic;
   40        almost_empty: OUT std_logic;
   41        wr_data_count: OUT std_logic_vector(1 downto 0)
   42      );
   43    end component;
   44  
   45    signal InternReset: std_logic;
   46    signal InternCount: std_logic_vector(1 downto 0);
   47  
   48  begin
   49  
   50    InternReset <= not Rst_n;
   51    HFull <= InternCount(1); 
   52  
   53    uc1: fifo15w32
   54    port map (
   55      din => D,
   56      wr_en => WrReq,
   57      wr_clk => WClk,
   58      rd_en => RdReq,
   59      rd_clk => RClk,
   60      rst => InternReset,
   61      dout => Q,
   62      full => open,
   63      empty => Empty,
   64      almost_full => AFull,
   65      almost_empty => open,
   66      wr_data_count => InternCount
   67      );
   68  
   69  end architecture a0 ; -- of FIFO15w
   70  
   71